BT848 ETC, BT848 Datasheet - Page 89
BT848
Manufacturer Part Number
BT848
Description
Single-Chip Video Capture for PCI
Manufacturer
ETC
Datasheet
1.BT848.pdf
(141 pages)
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Ground Planes
The layout should be optimized for lowest noise on the Bt848 power and ground
lines by shielding the digital inputs/outputs and providing good decoupling. The
lead length between groups of power and ground pins should be minimized to re-
duce inductive ringing.
The ground plane area should encompass all Bt848 ground pins, voltage reference
circuitry, power supply bypass circuitry for the Bt848, the analog input traces, any
input amplifiers, and all the digital signal traces leading to the Bt848.
The layout for the ground plane should be such that the two planes are at the same
electrical potential, but they should be isolated from each other in the areas sur-
rounding the chip. Also, the return path for current should be through the digital
plane. See Figure 38.
Figure 38. Example Ground Plane Layout
PC B
C
The Bt848 has digital grounds (GND) and analog grounds (AGND and VNEG).
ONSIDERATIONS
OARD
L848A_A
L
AYOUT
Ground Return
(i.e. PCI Bus Connection)
41
1
Ground
Analog
Ground
Bt848
Digital
121
81
79
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