BT848 ETC, BT848 Datasheet - Page 55

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
Physical Implementation
FIFO Input/Output Rates
®
VDFC has no responsibility for FIFO overruns. The DMA Controller will be able
to resynchronize to data streams that are shorter or longer than expected.
same time if a bus access latency persists across a FIELD transition, or if packed
VBI data proceeds planar YCrCb data.
The three FIFO outputs are delivered in parallel so that the DMA Controller can
monitor the FIFOs and perform skipping (reading and discarding data), if neces-
sary, on all three simultaneously.
FIFO, a FIFO Full (FFULL) condition is indicated prior to the FIFO count reach-
ing the maximum FIFO size. The FIFO is considered FFULL when the FIFO
Count (FCNT) value equals or exceeds the FFULL value.
and will be overwritten. The maximum bus latencies for various video formats and
modes are shown in Table 10.
The input and output ports of the Bt848’s FIFO can operate simultaneously and are
asynchronous to one another.
17.73 MHz. However, there will never be consecutive-pixel-cycle writes to the
same FIFO. The fastest FIFO write sequence is F1, F2, F1, F3. Therefore, the fast-
est write rate to any FIFO is less than or equal to half of the pixel rate.
MHz). All three FIFOs can be read simultaneously. Some bus systems may be de-
signed with PCI clocks slower than 33 MHz. The Bt848 data FIFO only supports
systems where the maximum input data rate is less than the output data rate. It can
support a input video clock (17.73 MHz) faster than the PCI clock (16 MHz) as
long as the video data rate does not exceed the available PCI burst rate.
The DMA Controller will guarantee that the FIFO does not fill, therefore the
Note that planar mode and packed mode data can be present in the FIFOs at the
Due to the latency in determining the number of DWORDs placed in each
A read must occur on the same cycle as FFULL, otherwise data will overflow
The maximum FIFO input rate would be for consecutive writes of PAL video at
The maximum FIFO output read rate is one FIFO word at the PCI clock rate (33
FSIZE1 = 70
FSIZE2 = 35
FSIZE3 = 35
FSIZET = 140
L848A_A
FFULL1 = 68
FFULL2 = 34
FFULL3 = 34
FFULLT = 136
Video and Control Data FIFO
F
UNCTIONAL
D
ESCRIPTION
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