BT848 ETC, BT848 Datasheet - Page 17

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
Pin Descriptions
Table 2 provides a description of pin functions, grouped by common function, Table 3 is a list of pin names in
pin-number order, and Figure 3 shows the pinout diagram.
NOTE:
Table 2. Pin Descriptions Grouped by Pin Function (1 of 6)
Brooktree
Pin #
11
9
13
28
15–17,
20–24,
29–32,
35–38,
53–55,
58–62,
66–69,
72–75
27, 39,
52, 65
Pins with alternate definitions on the Bt848A and Bt849A are indicated by shading
®
Pin Name
CLK
RST
GNT
IDSEL
AD[31:0]
CBE[3:0]
I/O
I
I
I
I
I/O
I/O
Signal
Clock
Reset
Grant
Initialization Device
Select
Address/Data
Bus Com-
mand/Byte
Enables
PCI Interface (50 pins)
L848A_A
Description
This input provides timing for all PCI transactions. All PCI sig-
nals except RST and INTA are sampled on the rising edge of
CLK, and all other timing parameters are defined with respect
to this edge. The Bt848 supports a PCI clock of up to
33.333333 MHz.
This input three-states all PCI signals asynchronous to the
CLK signal.
Agent granted bus.
This input is used to select the Bt848 during configuration
read and write transactions.
These three-state, bi-directional, I/O pins transfer both
address and data information. A bus transaction consists of
an address phase followed by one or more data phases for
either read or write operations.
first asserted. During the address phase, AD[31:0] contains a
byte address for I/O operations and a DWORD address for
configuration and memory operations. During data phases,
AD[7:0] contains the least significant byte and AD[31:24] con-
tains the most significant byte.
write data is stable and valid when IRDY is asserted. Data is
transferred during the clocks when both TRDY and IRDY are
asserted.
These three-state, bi-directional, I/O pins transfer both bus
command and byte enable information. During the address
phase of a transaction, CBE[3:0] contain the bus command.
During the data phase, CBE[3:0] are used as byte enables.
The byte enables are valid for the entire data phase and
determine which byte lanes carry meaningful data. CBE[3]
refers to the most significant byte and CBE[0] refers to the
least significant byte.
The address phase is the clock cycle in which FRAME is
Read data is stable and valid when TRDY is asserted and
F
UNCTIONAL
Pin Descriptions
D
ESCRIPTION
7