BT848 ETC, BT848 Datasheet - Page 124

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

C
Interrupt Mask
Interrupt Mask
Memory Mapped Location 0x104 – (INT_MASK)
RISC Program Counter
Memory Mapped Location 0x120 – (RISC_COUNT)
RISC Program Start Address
Memory Mapped Location 0x114 – (RISC_STRT_ADD)
114
Bits
Bits
Bits
ONTROL
[22:0]
[31:0]
[31:0]
[23]
R
EGISTER
Type
Type
Type
RW
RW
RW
RO
D
Default
0x000000
0
Default
Default
0x00000000
EFINITIONS
Name
RISC_PC
Name
RISC_IPC
Name
ETBF
Description
A value of 1 enables the interrupt bit. The bits correspond to the
same bits in the Interrupt Status register. Unmasking a bit may
generate an interrupt immediately due to a previously pending
condition. The PCI INTA is level sensitive. It remains asserted until
the device driver clears or masks the pending request.
Description
Base address for the RISC program. Standard 32-bit memory
space byte address, although the software must DWORD align by
setting the lowest two bits to 00. The DMA controller begins exe-
cuting pixel instructions at this address when RISC_ENABLE is
set, i.e. the RISC program counter is loaded with this pointer at the
rising edge of RISC_ENABLE.
Description
The current value of the RISC program counter. This may be
slightly ahead of the current instruction due to pre-fetching instruc-
tions into the queue.
0 = Normal operation
1 = Enable TritonI PCI controller compatibility.
L848A_A
Single-Chip Video Capture for PCI
Bt848/848A/849A
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