BT848 ETC, BT848 Datasheet - Page 58

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

F
DMA Controller
Figure 23. RISC Block Diagram
48
UNCTIONAL
From
FIFO
RISC Program
Target Memory
D
Start Address
Output [31:0]
ESCRIPTION
FIFO Status
FIFO Read
Number of
Available
Signals
in FIFO
FIFO
Bytes
Bits
The Bt848’s FIFO DWORDs are perfectly aligned to the PCI bus, i.e. bit 0 of the
FIFO DWORDs lines up with bit AD[0] on the PCI bus. Thus, video scan line data
is aligned to target memory locations, and data path combinational logic between
the FIFO and the PCI bus is not required.
menting, and contiguous. For a 1024-pixel scan line a maximum of 4 KB of con-
tiguous physical memory is required. Each scan line can be stored anywhere in the
32-bit address space. A scan line can be broken into segments with each segment
sent to a different target area. An image buffer can be allocated to line fragments
anywhere in the physical memory, as the line sequence is arbitrary.
Decoder
RISC
The target memory for a given scan line of data is assumed to be linear, incre-
DMA Controller
Code
Op
L848A_A
Address/Data
Control Signals
Byte Counter
Instruction
FIFO Data
Program
Decoder
Address
Counter
Buffer
Buffer
RISC
RISC
DMA
and
RISC
Instructions
Pixel Data [31:0]
Address
Single-Chip Video Capture for PCI
Initiator
PCI
Bt848/848A/849A
To PCI Bus
Interface
Brooktree
®