BT848 ETC, BT848 Datasheet - Page 80

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

E
General Purpose I/O Port
Table 13. Synchronous Pixel Interface (SPI) GPIO Signals
70
LECTRICAL
GPIO
[15:8]
[7:0]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
I
HRESET
VRESET
HACTIVE
DVALID
CBFLAG
FIELD
VACTIVE
VBISEL
Y[7:0]
CrCb[7:0]
NTERFACES
Signal
A 64-clock-long active low pulse. It is output following the rising edge of
CLKx1. The falling edge of HRESET indicates the beginning of a new video
line.
An active low signal that is at least two lines long (for non-VCR sources,
VRESET is normally six lines long). It is output following the rising edge of
CLKx1. The falling edge of VRESET indicates the beginning of a new field of
video output. The falling edge of VRESET lags the falling edge of HRESET
by two clock cycles at the start of an odd field. At the start of even fields, the
falling edge of VRESET is in the middle of a scan line, horizontal count
(HPIXEL/2)+1, on scan line 263 for NTSC and scan line 313 for PAL.
An active high signal that indicates the beginning of the active video and is
output following the rising edge of CLKx1. The HACTIVE flag is used to indi-
cate where nonblanking pixels are present. The start and the end of the
HACTIVE signal can be adjusted by programming the HDELAY and HAC-
TIVE registers.
An active high pixel qualifier that indicates whether or not the associated
pixel is valid. DVALID is independent of the HACTIVE and VACTIVE signals.
DVALID indicates which pixels are valid. DVALID will toggle high outside of
the active window, indicating a valid pixel outside the programmed active
region.
An active high pulse that indicates when Cb data is being output on the
chroma stream. During invalid pixels, CBFLAG holds the value of the last
valid pixel.
When high, indicates that an even field (field 2) is being output; when low it
indicates that an odd field (field 1) is being output. The transition of FIELD is
synchronous with the end of active video (i.e. the trailing edge of ACTIVE).
The same information can also be derived by latching the HRESET signal
with VRESET.
An active high signal that indicates the beginning of the active video and is
output following the rising edge of CLKx1. The VACTIVE flag is used to indi-
cate where nonblanking pixels are present. The start and the end of the VAC-
TIVE signal can be adjusted by programming the VDELAY and VACTIVE
registers.
An active high signal that indicates the beginning and end of the vertical
blanking interval. The end of VBISEL will adjust accordingly when VDELAY is
changed.
Digital pins for the luminance component of the video data stream.
Digital pins for the chrominance component of the video data stream
L848A_A
Description
Single-Chip Video Capture for PCI
Bt848/848A/849A
Brooktree
Number
110–117
92–99
Pin
82
83
84
85
86
87
88
89
®