BT848 ETC, BT848 Datasheet - Page 91

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
Latch-up Avoidance
®
Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by
static or impulse voltages on any signal input pin exceeding the voltage on the
power pins by more than 0.5 V, or falling below the GND pins by more than 0.5 V.
Latch-up can also occur if the voltage on any power pin exceeds the voltage on any
other power pin by more than 0.5 V.
pear more sensitive to latch-up. In reality, this is not the case. However, mixed sig-
nal devices tend to interact with peripheral devices such as video monitors or
cameras that are referenced to different ground potentials, or apply voltages to the
device prior to the time that its power system is stable. This interaction sometimes
creates conditions amenable to the onset of latch-up.
taken:
Figure 39. Optional Regulator Circuitry
S
In some cases, devices with mixed signal interfaces, such as the Bt848, can ap-
To maintain a robust design with the Bt848, the following precautions should be
YSTEM
•
•
•
•
(+12 V)
Apply power to the device before or at the same time as the interface cir-
cuitry.
Do not apply voltages below GND–0.5 V, or higher than VAA+0.5 V to
any pin on the device. Do not use negative supply op-amps or any other
negative voltage interface circuitry. All logic inputs should be held low
until power to the device has settled to the specified tolerance.
Connect all VDD, VAA and VPOS pins together through a low imped-
ance plane.
Connect all GND, AGND and VNEG pins together through a low imped-
ance plane.
P
OWER
L848A_A
S
R
UGGESTED PART NUMBERS
EGULATOR
I
N
GND
G
ROUND
T
O
EXAS
UT
I
NSTRUMENTS
(+5 V)
VAA,VDD
:
PC B
D
THE CURRENT REQUIREMENTS
OF THE
PERIPHERAL CIRCUITRY
OARD
IODES MUST HANDLE
A78 MO5M
Bt848
L
AYOUT
AND THE
Latch-up Avoidance
S
C
YSTEM
ONSIDERATIONS
(+5 V)
P
OWER
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