S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 133
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S9S12P64J0CFT
Manufacturer Part Number
S9S12P64J0CFT
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFT
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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5.1.2.3
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3
A block diagram of the BDM is shown in
5.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
Freescale Semiconductor
System
Host
External Signal Description
Block Diagram
Low-Power Modes
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
UNSEC
TRACE
SDV
Interface
The communication rate of this pin is based on the settings for the VCO clock
Serial
S12P-Family Reference Manual, Rev. 1.13
Control
Data
Figure 5-1. BDM Block Diagram
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
5-1.
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
133
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