S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 172
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S9S12P64J0CFT
Manufacturer Part Number
S9S12P64J0CFT
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFT
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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S12S Debug Module (S12SDBGV2)
6.3.2.8.4
Read: Anytime. See
Write: If DBG not armed. See
6.3.2.8.5
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
172
Address: 0x002B
Address: 0x002C
Bit[15:8]
Bits[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
Bit 15
Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the
selected comparator compares the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Bit 7
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator compares the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
0
0
7
7
Debug Comparator Address Low Register (DBGXAL)
Debug Comparator Data High Register (DBGADH)
Figure 6-18. Debug Comparator Address Low Register (DBGXAL)
Table 6-24
Figure 6-19. Debug Comparator Data High Register (DBGADH)
Bit 14
Bit 6
0
0
6
6
Table 6-24
for visible register encoding.
Table 6-26. DBGXAM Field Descriptions
Table 6-27. DBGXAL Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Bit 13
Bit 5
0
0
5
5
for visible register encoding.
Bit 12
Bit 4
0
0
4
4
Description
Description
Bit 11
Bit 3
0
0
3
3
Bit 10
Bit 2
0
0
2
2
Freescale Semiconductor
Bit 1
Bit 9
0
0
1
1
Bit 0
Bit 8
0
0
0
0
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