S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 226
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S9S12P64J0CFT
Manufacturer Part Number
S9S12P64J0CFT
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFT
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.17
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
Read: Anytime
Write: If APIFE=0, then write anytime, else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
226
0x02F4
0x02F5
APIR[15:0]
Reset
Reset
Field
15-0
W
W
R
R
APICLK=0: Period = 2*(APIR[15:0] + 1) * f
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
APIR15
APIR7
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
Table 7-19
Figure 7-21. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
Figure 7-22. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
0
0
7
7
= Unimplemented or Reserved
for details of the effect of the autonomous periodical interrupt rate bits.
APIR14
APIR6
Table 7-18. CPMUAPIRH / CPMUAPIRL Field Descriptions
0
0
6
6
S12P-Family Reference Manual, Rev. 1.13
APIR13
APIR5
0
0
5
5
APIR12
APIR4
0
0
4
4
ACLK
Description
APIR11
APIR3
0
0
3
3
APIR10
APIR2
0
0
2
2
Freescale Semiconductor
APIR9
APIR1
0
0
1
1
APIR8
APIR0
0
0
0
0
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