S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 388

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S9S12P64J0CFT

Manufacturer Part Number
S9S12P64J0CFT
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P64J0CFT

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Serial Communication Interface (S12SCIV5)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.
summarizes the results of the stop bit samples.
In
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
388
Figure 11-22
Table 11-18
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit (logic 0).
the verification samples RT3 and RT5 determine that the first low detected was noise and
RT8, RT9, and RT10 Samples
RT8, RT9, and RT10 Samples
summarizes the results of the data bit samples.
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
S12P-Family Reference Manual, Rev. 1.13
Table 11-18. Data Bit Recovery
Table 11-19. Stop Bit Recovery
NOTE
Data Bit Determination
Framing Error Flag
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
0
Noise Flag
Noise Flag
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
Freescale Semiconductor
Table 11-19

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