S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 444

• Manufacturer Part Number: S9S12P64J0CFT
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFT

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

128 KByte Flash Module (S12FTMRC128K1V1)
13.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed. Table 13-20 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
13.3.2.10 D-Flash Protection Register (DFPROT)
The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte
in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see
as indicated by reset condition F in
during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be unprotected,
then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the
444
Offset Module Base + 0x0009
Reset
W
R
DPOPEN
F
7
P-Flash Protection Restrictions
1. Allowed transitions marked with X, see
Protection
Scenario
From
= Unimplemented or Reserved
0
1
2
3
4
5
6
7
0
0
6
Table 13-20. P-Flash Protection Scenario Transitions
Figure 13-15. D-Flash Protection Register (DFPROT)
X
X
0
S12P-Family Reference Manual, Rev. 1.13
Figure
0
0
5
X
X
X
X
1
13-15. To change the D-Flash protection that will be loaded
X
X
X
X
2
To Protection Scenario
0
0
4
Figure 13-14
3
X
X
X
X
X
X
X
X
X
X
X
X
4
for a definition of the scenarios.
F
3
(1)
X
X
5
F
2
X
X
6
DPS[3:0]
Freescale Semiconductor
X
7
F
1
Table
F
0
13-3)