S9S12P64J0CFT Freescale Semiconductor, S9S12P64J0CFT Datasheet - Page 314
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S9S12P64J0CFT
Manufacturer Part Number
S9S12P64J0CFT
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFT
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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Analog-to-Digital Converter (ADC12B10C)
9.3.2.4
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
314
Module Base + 0x0003
ACMPIE
ASCIE
Reset
Field
1
0
W
R
DJM
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
ATD Control Register 3 (ATDCTL3)
0
7
Interrupt will be requested whenever any of the respective CCF flags is set.
= Unimplemented or Reserved
S8C
0
6
ETRIGLE
Table 9-6. ATDCTL2 Field Descriptions (continued)
Figure 9-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 9-7. External Trigger Configurations
S12P-Family Reference Manual, Rev. 1.13
S4C
1
5
ETRIGP
0
1
0
1
S2C
0
4
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
FIFO
0
2
Freescale Semiconductor
FRZ1
0
1
FRZ0
0
0
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