S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 1159
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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29.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
Freescale Semiconductor
MGSTAT[1:0]
MGBUSY
ACCERR
Offset Module Base + 0x0007
Reset
FPVIOL
RSVD
Field
CCIF
1–0
7
5
4
3
2
W
R
ERSERIF
Flash Error Status Register (FERSTAT)
7
0
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
= Unimplemented or Reserved
PGMERIF
0
6
Figure 29-12. Flash Error Status Register (FERSTAT)
Description,” and
MC9S12XE-Family Reference Manual Rev. 1.25
Table 29-17. FSTAT Field Descriptions
0
0
5
Section 29.6,
EPVIOLIF
0
4
Description
“Initialization” for details.
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
ERSVIF1
.
0
3
Section
ERSVIF0
0
2
29.4.1.2) or issuing an illegal Flash
DFDIF
0
1
Section 29.4.2,
SFDIF
0
0
.
1159
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