S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 321
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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8.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
8.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Read: Anytime. See
Freescale Semiconductor
Address: 0x0028
Address: 0x0028
0x002C
0x002D
0x002A
0x002B
0x002E
0x002F
0x0028
0x0029
Reset
Reset
W
W
R
R
SZE
Comparator Register Descriptions
0
0
0
7
7
Debug Comparator Control Register (DBGXCTL)
Figure 8-13. Debug Comparator Control Register (Comparators A and C)
Figure 8-14. Debug Comparator Control Register (Comparators B and D)
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
Table 8-29
= Unimplemented or Reserved
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
NDB
SZ
0
0
6
6
CONTROL
MC9S12XE-Family Reference Manual Rev. 1.25
for visible register encoding.
Table 8-28. Comparator Register Layout
TAG
TAG
0
0
5
5
BRK
BRK
0
0
4
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
RW
RW
0
0
3
3
Chapter 8 S12X Debug (S12XDBGV3) Module
RWE
RWE
0
0
2
2
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
SRC
SRC
0
0
1
1
COMPE
COMPE
0
0
0
0
321
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