S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 511

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

13.3.2.3
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
ETRIGLE
ICLKSTP
ETRIGP
ETRIGE
Reset
AFFC
Field
6
5
4
3
2
W
R
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode
and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.
Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus
frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits
PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic
compare interrupt or the sequence complete interrupt can be used to inform software handler about changing
A/D values. External trigger will not work while converting in stop mode. For conversions during transition from
Run to Stop Mode or vice versa the result is not written to the results register, no CCF flag is set and no compare
is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time t
switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be
1 A/D continues to convert in stop mode using internally generated clock (ICLK)
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 13-8
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external
events. External trigger will not work while converting in stop mode.
0 Disable external trigger
1 Enable external trigger
ATD Control Register 2 (ATDCTL2)
0
0
7
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
aborted and automatically restarted when exiting stop mode.
= Unimplemented or Reserved
for details.
AFFC
0
6
Figure 13-5. ATD Control Register 2 (ATDCTL2)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-7. ATDCTL2 Field Descriptions
ICLKSTP
0
5
Table
13-6. If external trigger source is one of the AD channels, the digital input
ETRIGLE
0
4
Description
ETRIGP
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
0
3
ETRIGE
0
2
ATDSTPRCV
ASCIE
0
1
Table 13-8
is required to
ACMPIE
for details.
0
0
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