S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 390

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 10 XGATE (S12XGATEV3)
ADD
Operation
RS1 + RS2
RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #IMM16[15:8])
Performs a 16 bit addition and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
390
N:
Z:
V:
C:
ADD RD, RS1, RS2
ADD RD, #IMM16
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Refer to ADDH instruction for #IMM16 operations.
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Refer to ADDH instruction for #IMM16 operations.
Z
∆
V
∆
Source Form
⇒ RD
When using immediate addressing mode (ADD RD, #IMM16), the V-flag
and the C-Flag of the first instruction (ADDL RD, #IMM16[7:0]) are not
considered by the second instruction (ADDH RD, #IMM16[15:8]).
⇒ Don’t rely on the V-Flag if RD + IMM16[7:0] ≥ 2
⇒ Don’t rely on the C-Flag if RD + IMM16[7:0] ≥ 2
C
∆
new
MC9S12XE-Family Reference Manual Rev. 1.25
| RS1[15] & RS2[15] & RD[15]
TRI
IMM8
IMM8
Address
Mode
new
| RS2[15] & RD[15]
Add without Carry
0
1
1
NOTE
0
1
1
0
1
1
1
0
0
new
new
1
0
1
Machine Code
RD
RD
RD
15
16
.
.
RS1
IMM16[15:8]
IMM16[7:0]
RS2
Freescale Semiconductor
ADD
1
0
Cycles
P
P
P