S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 385
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.8.1.13 Index Register plus Register Offset (IDR)
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
10.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
10.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
10.8.2
10.8.2.1
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
The same set of modes is available for the store instructions
Freescale Semiconductor
LDB
STW
LDB
STW
LDB
STW
LDL
LDW
LDB
STB
STW
Instruction Summary and Usage
Load & Store Instructions
R4,(R1,R2)
R4,(R1,R2)
R4,(R1,R2+)
R4,(R1,R2+)
R4,(R1,-R2)
R4,(R1,-R2)
RD,#IMM8
RD,(RB,RI)
RD,(RB, RI+)
RS,(RB, RI)
RS,(RB, RI+)
MC9S12XE-Family Reference Manual Rev. 1.25
; loads a byte from (R1+R2) into R4
; stores R4 as a word to (R1+R2)
; loads a byte from (R1+R2) into R4, R2+=1
; stores R4 as a word to (R1+R2), R2+=2
; R2 -=1, loads a byte from (R1+R2) into R4
; R2 -=2, stores R4 as a word to (R1+R2)
; loads an immediate 8 bit value to the lower byte of RD
; loads data using RB+RI as effective address
; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
; stores data using RB+RI as effective address
; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.
Chapter 10 XGATE (S12XGATEV3)
385
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