S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 165
S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1. Read: Anytime.
1. Read: Anytime.
2.3.87
2.3.88
Freescale Semiconductor
Address 0x036A
Address 0x036B
Write: Anytime.
Write: Anytime.
DDRR
Field
Reset
Reset
7-0
W
W
R
R
Port R data direction—
This register controls the data direction of pins 7 through 0.
The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRR7
RDRR7
Port R Data Direction Register (DDRR)
Port R Reduced Drive Register (RDRR)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
DDRR6
RDRR6
0
0
6
6
Figure 2-86. Port R Reduced Drive Register (RDRR)
Figure 2-85. Port R Data Direction Register (DDRR)
Table 2-83. DDRR Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDRR5
RDRR5
0
0
5
5
DDRR4
RDRR4
NOTE
0
0
4
4
Description
DDRR3
RDRR3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRR2
RDRR2
0
0
2
2
Access: User read/write
Access: User read/write
DDRR1
RDRR1
0
0
1
1
DDRR0
RDRR0
0
0
0
0
165
(1)
(1)
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