S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 558

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
All bits reset to zero.
558
BUFFEN
TFMOD
PACMX
LATQ
Field
SHxy
7:4
3
2
1
0
Share Input action of Input Capture Channels x and y
0 Normal operation
1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge
Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers
are emptied, an input capture event will first update the related input capture register with the main timer
contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF
interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on ICx.
0 The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin
1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 are set only when a latch
8-Bit Pulse Accumulators Maximum Count
0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,
1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value
IC Buffer Enable
0 Input capture and pulse accumulator holding registers are disabled.
1 Input capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ
Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC
and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled.
Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and
pulse accumulators registers into their holding registers.
0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input
1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is
detector is used to be active on the channel ‘y’.
occurs.
on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD = 0.
it will be incremented to 0x0000.
0x00FF indicates a count of 255 or more.
control bit.
pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding
register and the IC register memorizes the new timer value.
written into the count register MCCNT (see
the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse
accumulators are cleared.
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-31. ICSYS Field Descriptions
Section 14.4.1.1.2, “Buffered IC
Description
Channels”). With a latching event
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