C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet
C8051T622-GMR
Specifications of C8051T622-GMR
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C8051T622-GMR Summary of contents
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... PCA Timer 0 USB Controller / Timer 1 Timer 2 Transceiver Timer 3 LOW FREQUENCY INTERNAL OSCILLATOR 48 MHz PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 16/8 KB 8051 CPU EPROM (48 MIPS) FLEXIBLE DEBUG CIRCUITRY INTERRUPTS Copyright © 2011 by Silicon Laboratories Port 0 Port 1 P2.0 1280 B SRAM POR WDT C8051T622/3 and C8051T326/7 ...
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... C8051T622/3 and C8051T326/7 2 Rev. 1.1 ...
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... MCU Interrupt Sources and Vectors................................................................ 60 12.1.1. Interrupt Priorities.................................................................................... 61 12.1.2. Interrupt Latency ..................................................................................... 61 12.2. Interrupt Register Descriptions ........................................................................ 61 12.3. INT0 and INT1 External Interrupt Sources ...................................................... 69 13. Program Memory (EPROM)................................................................................... 71 13.1. Programming the EPROM Memory................................................................. 71 13.1.1. EPROM Programming over the C2 Interface.......................................... 71 13.1.2. EPROM In-Application Programming...................................................... 72 13.2. Security Options .............................................................................................. 73 13.3. EPROM Writing Guidelines ............................................................................. 73 C8051T622/3 and C8051T326/7 Rev. 1.1 3 ...
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... C8051T622/3 and C8051T326/7 13.3.1. VDD Maintenance and the VDD monitor ................................................ 73 13.3.2. PSWE Maintenance ................................................................................ 74 13.3.3. System Clock .......................................................................................... 74 13.4. Program Memory CRC .................................................................................... 74 13.4.1. Performing 32-bit CRCs on Full EPROM Content .................................. 74 13.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks............................ 74 14. Power Management Modes................................................................................... 77 14.1. Idle Mode......................................................................................................... 77 14.2. Stop Mode ....................................................................................................... 78 14.3. Suspend Mode ................................................................................................ 78 15. Reset Sources ........................................................................................................ 80 15 ...
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... Software ACK Generation ............................................................ 156 19.4.2.2. Hardware ACK Generation ........................................................... 156 19.4.3. Hardware Slave Address Recognition .................................................. 158 19.4.4. Data Register ........................................................................................ 161 19.5. SMBus Transfer Modes................................................................................. 162 19.5.1. Write Sequence (Master) ...................................................................... 162 19.5.2. Read Sequence (Master) ...................................................................... 163 19.5.3. Write Sequence (Slave) ........................................................................ 164 19.5.4. Read Sequence (Slave) ........................................................................ 165 19.6. SMBus Status Decoding................................................................................ 165 C8051T622/3 and C8051T326/7 Rev. 1.1 5 ...
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... C8051T622/3 and C8051T326/7 20. UART0 ................................................................................................................... 171 20.1. Enhanced Baud Rate Generation.................................................................. 172 20.2. Operational Modes ........................................................................................ 173 20.2.1. 8-Bit UART ............................................................................................ 173 20.2.2. 9-Bit UART ............................................................................................ 174 20.3. Multiprocessor Communications ................................................................... 175 21. UART1 ................................................................................................................... 179 21.1. Baud Rate Generator .................................................................................... 179 21.2. Data Format................................................................................................... 180 21.3. Configuration and Operation ......................................................................... 181 21.3.1. Data Transmission ................................................................................ 182 21.3.2. Data Reception ..................................................................................... 182 21 ...
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... Pulse Width Modulator Mode.................................................... 234 24.4. Watchdog Timer Mode .................................................................................. 235 24.4.1. Watchdog Timer Operation ................................................................... 235 24.4.2. Watchdog Timer Usage ........................................................................ 236 24.5. Register Descriptions for PCA0..................................................................... 237 25. C2 Interface .......................................................................................................... 244 25.1. C2 Interface Registers................................................................................... 244 25.2. C2 Pin Sharing .............................................................................................. 252 Document Change List.............................................................................................. 253 Contact Information................................................................................................... 254 C8051T622/3 and C8051T326/7 Rev. 1.1 7 ...
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... Figure 1.2. Typical Bus-Powered Connections for the C8051T622/3 and C8051T326 ........................................................................................... 17 Figure 1.3. Typical Bus-Powered Connections for the C8051T327 ........................ 17 Figure 3.1. C8051T622/3 (QFN-24) Pinout Diagram (Top View) ............................ 21 Figure 3.2. C8051T326 (QFN-28) Pinout Diagram (Top View) ............................... 22 Figure 3.3. C8051T327 (QFN-28) Pinout Diagram (Top View) ............................... 23 Figure 4.1. QFN-24 Package Drawing .................................................................... 24 Figure 4 ...
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... Figure 24.7. PCA Frequency Output Mode ........................................................... 232 Figure 24.8. PCA 8-Bit PWM Mode Diagram ........................................................ 233 Figure 24.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 234 Figure 24.10. PCA 16-Bit PWM Mode ................................................................... 235 Figure 24.11. PCA Module 2 with Watchdog Timer Enabled ................................ 236 Figure 25.1. Typical C2 Pin Sharing ...................................................................... 252 C8051T622/3 and C8051T326/7 Rev. 1.1 9 ...
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... C8051T622/3 and C8051T326/7 List of Tables Table 2.1. Product Selection Guide ......................................................................... 18 Table 3.1. Pin Definitions for the C8051T622/3 and C8051T326/7 ......................... 19 Table 4.1. QFN-24 Package Dimensions ................................................................ 24 Table 4.2. QFN-24 PCB Land Pattern Dimesions ................................................... 25 Table 5.1. QFN-28 Package Dimensions ................................................................ 26 Table 5.2. QFN-28 PCB Land Pattern Dimensions ................................................. 27 Table 6.1. Absolute Maximum Ratings .................................................................... 28 Table 6 ...
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... Table 24.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules ................................................................ 228 Table 24.3. Watchdog Timer Timeout Intervals1 ................................................... 237 C8051T622/3 and C8051T326/7 Rev. 1.1 11 ...
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... C8051T622/3 and C8051T326/7 List of Registers SFR Definition 7.1. REG01CN: Voltage Regulator Control .......................................... 39 SFR Definition 8.1. DPL: Data Pointer Low Byte .......................................................... 46 SFR Definition 8.2. DPH: Data Pointer High Byte ......................................................... 46 SFR Definition 8.3. SP: Stack Pointer ........................................................................... 47 SFR Definition 8.4. ACC: Accumulator ......................................................................... 47 SFR Definition 8. Register .................................................................................. 47 SFR Definition 8.6. PSW: Program Status Word .......................................................... 48 SFR Definition 9 ...
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... SFR Definition 21.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 187 SFR Definition 21.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 188 SFR Definition 22.1. SPI0CFG: SPI0 Configuration ................................................... 196 SFR Definition 22.2. SPI0CN: SPI0 Control ............................................................... 197 SFR Definition 22.3. SPI0CKR: SPI0 Clock Rate ....................................................... 198 C8051T622/3 and C8051T326/7 High Byte ................................................................... 147 Rev. 1.1 13 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 22.4. SPI0DAT: SPI0 Data ................................................................. 198 SFR Definition 23.1. CKCON: Clock Control .............................................................. 203 SFR Definition 23.2. TCON: Timer Control ................................................................. 208 SFR Definition 23.3. TMOD: Timer Mode ................................................................... 209 SFR Definition 23.4. TL0: Timer 0 Low Byte ............................................................... 210 SFR Definition 23.5. TL1: Timer 1 Low Byte ............................................................... 210 SFR Definition 23 ...
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... USB communication. An additional internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant of input signals The C8051T622/3 are available in 24-pin QFN packaging and the C8051T326/7 are available in 28-pin QFN packaging. See Table 2.1 for ordering infor- mation ...
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... System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator Clock Recovery USB Peripheral D+ Full / Low D- Speed Transceiver VBUS Figure 1.1. C8051T622/3 and C8051T326/7 Block Diagram 16 Port I/O Configuration CIP-51 8051 Digital Peripherals UART0 UART1 256 Byte SRAM Timers PCA/ WDT SMBus SPI ...
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... GROUND NET Pin 2 is the only required Ground connection on the device. The ground lug on the bottom of the device is used for heat dissipation, and is optional. Figure 1.2. Typical Bus-Powered Connections for the C8051T622/3 and C8051T326 SUPPLY NET Add decoupling/bypass 4.7µF capacitors close to each voltage supply pin ...
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... C8051T622/3 and C8051T326/7 2. Ordering Information Table 2.1. Product Selection Guide 1 C8051T622-GM 48 16k 1 C8051T623- C8051T326-GM 48 16k 3 1 C8051T327-GM 48 16k Notes: 1. 512 Bytes Reserved for Factory use. 2. Pin compatible with the C8051F326-GM. 3. Pin compatible with the C8051F327-GM. 18 1280 1280 Y ...
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... Pin Definitions Table 3.1. Pin Definitions for the C8051T622/3 and C8051T326/7 Pin Number Name ‘T622/3 ‘T326 ‘T327 GND RST C2CK P2. C2D REGIN VBUS XTAL1 ...
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... C8051T622/3 and C8051T326/7 Table 3.1. Pin Definitions for the C8051T622/3 and C8051T326/7(Continued) Pin Number Name ‘T622/3 ‘T326 ‘T327 P0. XTAL2 P0 P0 P0. P0. P1 P1 P1.6 11 — — 20 Type Description D I/O or Port 0 ...
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... C8051T622/3 and C8051T326/7 P0.0 1 GND 2 C8051T622/3- Top View D– 4 VIO 5 VDD 6 GND Figure 3.1. C8051T622/3 (QFN-24) Pinout Diagram (Top View) 18 P0.7 17 P1.0 16 P1.1 / VPP 15 P1.2 14 P1.3 13 P1.4 Rev. 1.1 21 ...
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... C8051T622/3 and C8051T326/7 ) P0.0 1 GND D– 4 VIO 5 VDD 6 REGIN 7 Figure 3.2. C8051T326 (QFN-28) Pinout Diagram (Top View) 22 C8051T326-GM Top View GND Rev. 1.1 21 N.C. 20 N.C. 19 P1.0 18 P1.1 / VPP 17 P1.2 P1 N.C ...
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... C8051T622/3 and C8051T326/7 P0.1 1 P0.0 2 GND 3 C8051T327- Top View D– 5 VDD 6 REGIN 7 Figure 3.3. C8051T327 (QFN-28) Pinout Diagram (Top View) 21 N.C. 20 N.C. 19 P1.0 18 P1.1 / VPP 17 P1.2 16 P1.3 GND 15 N.C Rev. 1.1 23 ...
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... C8051T622/3 and C8051T326/7 4. QFN-24 Package Specifications Figure 4.1. QFN-24 Package Drawing Table 4.1. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.55 2.70 e 0.50 BSC. E 4.00 BSC. E2 2.55 2.70 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2 and L which are toleranced per supplier designation ...
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... C8051T622/3 and C8051T326/7 Figure 4.2. QFN-24 Recommended PCB Land Pattern Table 4.2. QFN-24 PCB Land Pattern Dimesions Dimension Min Max C1 3.90 4.00 C2 3.90 4.00 E 0.50 BSC X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad ...
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... C8051T622/3 and C8051T326/7 5. QFN-28 Package Specifications Figure 5.1. QFN-28 Package Drawing Table 5.1. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. E2 2.90 3.15 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2 and L which are toleranced per supplier designation ...
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... C8051T622/3 and C8051T326/7 Figure 5.2. QFN-28 Recommended PCB Land Pattern Table 5.2. QFN-28 PCB Land Pattern Dimensions Dimension Min Max C1 4.80 C2 4.80 E 0.50 X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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... C8051T622/3 and C8051T326/7 6. Electrical Characteristics 6.1. Absolute Maximum Specifications Table 6.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during program- PP ming) with respect to GND Voltage on V with respect to PP GND during a programming oper- ation ...
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... Temperature Range SYSCLK (System Clock) (Note 2) Tsysl (SYSCLK low time) Tsysh (SYSCLK high time) Notes: 1. Analog performance is not guaranteed when 2. SYSCLK must be at least 32 kHz to enable debugging. C8051T622/3 and C8051T326/7 Min 1.8 1.75 = 1.8 V, Clock = 48 MHz = 1.8 V, Clock = 1 MHz = 3.45 V, Clock = 48 MHz = 3.45 V, Clock = 1 MHz = 3.6 V, Clock = 48 MHz = 3 ...
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... C8051T622/3 and C8051T326/7 Table 6.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Conditions Output High Voltage I = –10 µA, Port I/O push-pull –3 mA, Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage µ 8 Input High Voltage Input Low Voltage Input Leakage ...
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... Normal Mode (REG1MD = 0) Low Power Mode (REG1MD = 1) Notes: 1. Input range specified for regulation. When an external regulator is used, should be tied to 2. Output current is total regulator output, including any current required by the C8051T622/3 and C8051T326/7. 3. The minimum input voltage is 2 Table 6.6. EPROM Electrical Characteristics Parameter ...
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... C8051T622/3 and C8051T326/7 Table 6.7. Internal High-Frequency Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Conditions Oscillator Frequency IFCN = 11b Oscillator Supply Current 25 °C, V (from V ) OSCICN OSCICN Power Supply Sensitivity Constant Temperature ...
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... Full Speed Receiver Differential Input | (D+) - (D-) | Sensitivity ( Differential Input Common Mode Range ( Input Leakage Current (I ) Pullups Disabled L Note: Refer to the USB Specification for timing diagrams and symbol definitions. C8051T622/3 and C8051T326/7 Min 2.8 — 1.3 — — 1.425 0.2 0.8 — ...
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... C8051T622/3 and C8051T326/7 6.3. Typical Performance Curves Figure 6.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) Figure 6.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) 34 Rev. 1.1 ...
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... Voltage Regulators (REG0 and REG1) C8051T622/3 and C8051T326/7 devices include two internal voltage regulators: one regulates a voltage source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the V to power external devices ...
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... C8051T622/3 and C8051T326/7 VBUS From VBUS From 5 V REGIN Power Net VDD Power Net Figure 7.2. REG0 Configuration: USB Self-Powered VBUS From VBUS REGIN From 3 V Power Net Figure 7.3. REG0 Configuration: USB Self-Powered, Regulator Disabled Voltage Regulator (REG0 ...
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... C8051T622/3 and C8051T326/7 VBUS From 5 V REGIN Power Net VDD Power Net Figure 7.4. REG0 Configuration: No USB Connection VBUS Sense Voltage Regulator (REG0 Out Rev. 1.1 Device Power Net 37 ...
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... C8051T622/3 and C8051T326/7 7.2. Voltage Regulator (REG1) Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode. This allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the inter- nal power network of the device when the part enters STOP mode ...
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... Low Power Mode - Memory power controller enabled (EPROM turns on/off as needed). Note external clock source is used with the Memory Power Controller enabled, and the clock frequency changes from slow (< 2.0 MHz) to fast (> 2.0 MHz clocks may be "skipped" to ensure that the EPROM power is stable before reading memory. C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 8. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 ...
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... Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. C8051T622/3 and C8051T326/7 2 2/4 3 ...
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... C8051T622/3 and C8051T326/7 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct ...
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... Exchange low nibble of indirect RAM with A Boolean Manipulation CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit C8051T622/3 and C8051T326/7 Description Rev. 1.1 Bytes Clock Cycles ...
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... C8051T622/3 and C8051T326/7 Table 8.1. CIP-51 Instruction Set Summary(Continued) Mnemonic ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit Move direct bit to Carry MOV bit, C ...
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... Detailed descriptions of the remaining SFRs are included in the sec- tions of the datasheet associated with their corresponding system function. C8051T622/3 and C8051T326/7 Rev. 1.1 45 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 8.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x82 Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. SFR Definition 8.2. DPH: Data Pointer High Byte ...
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... This register is the accumulator for arithmetic operations. SFR Definition 8. Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] B Register. This register serves as a second accumulator for certain arithmetic operations. C8051T622/3 and C8051T326 SP[7:0] R Function ACC[7:0] R ...
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... C8051T622/3 and C8051T326/7 SFR Definition 8.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition bor- row (subtraction cleared to logic 0 by all other arithmetic operations. ...
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... Prefetch Engine The C8051T622/3 and C8051T326/7 family of devices incorporate a 2-byte prefetch engine. Because the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from EPROM memory two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute ...
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... Memory 0x0000 10.1. Program Memory The CIP-51 core has program memory space. The C8051T622/3 and C8051T326/7 implements 16384 or 8192 bytes of this program memory space as in-system byte-programmable EPROM organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF. Note: 512 bytes (0x3E00 – 0x3FFF) of this memory are reserved for factory use and are not available for user program storage ...
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... Data Memory The C8051T622/3 and C8051T326/7 device family includes 1280 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. 1024 bytes of this memory is on-chip “external” memory. The data memory map is shown in Figure 10.1 for reference. ...
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... CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 10.1 illustrates the data memory organization of the C8051T622/3 and C8051T326/7. ...
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... Accessing USB FIFO Space The C8051T622/3 and C8051T326/7 include 256 bytes of RAM which functions as USB FIFO space. Figure 10.3 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO registers; see Section “18.5. FIFO Management” on page 124 for more informa- tion on accessing these FIFOs ...
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... C8051T622/3 and C8051T326/7 0xFFFF On-Chip XRAM 0x0500 0x04FF Endpoint0 (64 bytes) 0x04C0 0x04BF Endpoint1 (128 bytes) 0x0440 0x043F Endpoint2 (64 bytes) 0x0400 0x03FF On-Chip XRAM 0x0000 Figure 10.3. USB FIFO Space and XRAM Memory Map with USBFAE set USB FIFO Space (USB Clock Domain) ...
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... XRAM space at addresses 0x0400 to 0x04FF. The USB clock must be active and greater than or equal to twice the SYSCLK (USBCLK > SYSCLK) to access this area with MOVX instructions. 5:0 Unused Unused. Read = 000011b; Write = Don’t Care C8051T622/3 and C8051T326 ...
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... SFRs used to configure and access the sub-systems unique to the C8051T622/3 and C8051T326/7. This allows the addition of new functionality while retaining com- patibility with the MCS-51™ instruction set. Table 11.1 lists the SFRs implemented in the C8051T622/3 and C8051T326/7 device family. ...
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... Port 0 Skip P0SKIP 0x90 Port 1 Latch P1 0xBA Port 1Mask Configuration P1MASK 0xB6 Port 1 Match Configuration P1MAT 0xF2 Port 1 Input Mode Configuration P1MDIN 0xA5 Port 1 Output Mode Configuration P1MDOUT C8051T622/3 and C8051T326/7 Description Rev. 1.1 Page 47 47 203 ...
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... C8051T622/3 and C8051T326/7 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xD5 Port 1 Skip P1SKIP 0xA0 Port 2 Latch P2 0xA6 Port 2 Output Mode Configuration P2MDOUT 0xD8 PCA Control PCA0CN 0xFC PCA Capture 0 High ...
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... USB0 Transceiver Control USB0XCN 0xFF V Monitor Control VDM0CN DD 0xE1 Port I/O Crossbar Control 0 XBR0 0xE2 Port I/O Crossbar Control 1 XBR1 0xE3 Port I/O Crossbar Control 2 XBR2 C8051T622/3 and C8051T326/7 Description Rev. 1.1 Page 161 185 47 196 198 197 198 208 211 211 210 210 209 ...
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... MCU Interrupt Sources and Vectors The C8051T622/3 and C8051T326/7 MCUs support 14 interrupt sources. Software can simulate an inter- rupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag ...
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... The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051T622/3 and C8051T326/7 Rev. 1.1 61 ...
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... C8051T622/3 and C8051T326/7 Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B USB0 0x0043 RESERVED 0x004B RESERVED 0x0053 Programmable Coun- 0x005B ...
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... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. 0 EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input. C8051T622/3 and C8051T326 ET2 ES0 ET1 R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 12.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1b, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. ...
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... This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. 0 ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051T622/3 and C8051T326 EPCA0 Reserved Reserved R/W R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 Reserved Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. ...
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... This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. 0 EVBUS Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. C8051T622/3 and C8051T326 EMAT Reserved R/W R/W R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xF7 Bit Name 7:4 Unused Unused. Read = 0000b, Write = Don't Care. 3 PMAT Port Match Interrupt Priority Control. This bit sets the priority of the Port Match Event interrupt. ...
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... IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051T622/3 and C8051T326/7 IT1 IN1PL 1 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. 6:4 IN1SL[2:0] INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to INT1. Note that this pin assignment is independent of the Crossbar ...
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... Program Memory (EPROM) C8051T622/3 and C8051T326/7 devices include on-chip byte-programmable EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special programming voltage is applied to the V programmed in system using an external capacitor on the V programmable only once (i.e. non-erasable). Table 6.6 on page 31 shows the EPROM specifications. ...
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... C8051T622/3 and C8051T326/7 13.1.2. EPROM In-Application Programming The EPROM of the C8051T622/3 and C8051T326/7 devices has an In-Application Programming option. In-Application Programming will be much slower than normal programming where the V voltage is applied to the V pin, but it allows a small number of bytes to be programmed anywhere in the PP non-reserved areas of the EPROM. In order to use this option, V ...
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... Security Options The C8051T622/3 and C8051T326/7 devices provide security options to prevent unauthorized viewing of proprietary program code and constants. A security byte stored at location 0x3FF8 in the EPROM address space can be used to lock the program memory from being read or written across the C2 interface. The lock byte can always be read regardless of the security settings. Table 13.1 shows the security byte decod- ing. Refer to “ ...
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... C8051T622/3 and C8051T326/7 example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. 13.3.2. PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set There should be exactly one routine in code that sets PSWE write EPROM bytes. ...
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... EPROM by writing a non-0xA5 value to MEMKEY from software. Read: When read, bits 1–0 indicate the current EPROM lock state. 00: EPROM is write locked. 01: The first key code has been written (0xA5). 10: EPROM is unlocked (writes allowed). 11: EPROM writes disabled until the next reset. C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 13.3. IAPCN: In-Application Programming Control Bit 7 6 IAPEN IAPDISD Name R/W R/W Type 0 0 Reset SFR Address = 0xF5 Bit Name 7 IAPEN In-Application Programming Enable. 0: In-Application Programming is disabled. 1: In-Application Programming is enabled. 6 IAPHWD In-Application Programming Hardware Disable. This bit disables the In-Application Programming hardware so the V pin can be used as a normal GPIO pin. Note: This bit should not be set less than 1 µ ...
Page 77
... Idle. Stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. SFR Definition 14.1 describes the Power Control Register (PCON) used to control the C8051T622/3 and C8051T326/7's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 16 ...
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... C8051T622/3 and C8051T326/7 vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi- nitely, waiting for an external stimulus to wake up the system. Refer to Section “15.5. PCA Watchdog Timer Reset” on page 83 for more information on the use and configuration of the WDT. ...
Page 79
... IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 15. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values ...
Page 81
... V RST RST Logic HIGH Logic LOW Power-On Reset Figure 15.2. Power-On and V C8051T622/3 and C8051T326/7 ramps from ramp time is 1 ms; slower ramp times may DD reaches the V level. For ramp times less than DD RST ) is typically less than 0.3 ms. ...
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... C8051T622/3 and C8051T326/7 15.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 15.2). When level above V , the CIP-51 will be released from the reset state. Note that even though internal data ...
Page 83
... WDT is enabled and clocked by SYSCLK / 12 following any reset system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The state of the RST pin is unaffected by this reset. C8051T622/3 and C8051T326/7 Monitor Control DD ...
Page 84
... C8051T622/3 and C8051T326/7 15.6. EPROM Error Reset If an EPROM program read or write targets an illegal address, a system reset is generated. This may occur due to any of the following: Programming hardware attempts to write or read an EPROM location which is above the user code space address limit. ...
Page 85
... WDTRSF Watchdog Timer Reset Flag. N/A 2 MCDRSF Missing Clock Detector Enable and Flag. 1 PORSF Power- Reset Flag, and V Reset Enable. 0 PINRSF HW Pin Reset Flag. Note: Do not use read-modify-write operations on this register C8051T622/3 and C8051T326 SWRSF WDTRSF MCDRSF R/W R Varies Varies Write Writing a 1 enables USB as a reset source ...
Page 86
... C8051T622/3 and C8051T326/7 16. Oscillators and Clock Selection C8051T622/3 and C8051T326/7 devices include a programmable internal high-frequency oscillator, a pro- grammable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-fre- quency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 16 ...
Page 87
... External Oscillator Note: Clock Recovery must be enabled for this configuration. Clock Signal USB Clock Internal Oscillator Clock Signal USB Clock External Oscillator C8051T622/3 and C8051T326/7 USB Full Speed (48 MHz) Internal Oscillator Input Source Selection Register Bit Settings Internal Oscillator* USBCLK = 000b Divide by 1 ...
Page 88
... C8051T622/3 and C8051T326/7 SFR Definition 16.1. CLKSEL: Clock Select Bit 7 6 USBCLK[2:0] Name R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7 Unused Unused. Read = 0b; Write = Don’t Care 6:4 USBCLK[2:0] USB Clock Source Select Bits. 000: USBCLK derived from the Internal High-Frequency Oscillator. ...
Page 89
... The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 16.2. On C8051T622/3 and C8051T326/7 devices, OSCICL is factory calibrated to obtain a 48 MHz base fre- quency. Note that the system clock may be derived from the programmed internal oscillator divided after a divide by 4 stage, as defined by the IFCN bits in register OSCICN ...
Page 90
... C8051T622/3 and C8051T326/7 SFR Definition 16.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. 6 IFRDY Internal H-F Oscillator Frequency Ready Flag. 0: Internal H-F Oscillator is not running at programmed frequency. ...
Page 91
... Clock Multiplier The C8051T622/3 and C8051T326/7 device includes a 48 MHz high-frequency oscillator instead MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high- frequency oscillator. For compatibility with the Flash development platform, however, the CLKMUL register (SFR Definition 16 ...
Page 92
... C8051T622/3 and C8051T326/7 16.5. Programmable Internal Low-Frequency (L-F) Oscillator All C8051T622/3 and C8051T326/7 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see SFR Definition 16.5). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’ ...
Page 93
... For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use the configuration shown in Figure 16.1, Option 1. With a stray capacitance per pin (6 pF total), the 13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 16.2. C8051T622/3 and C8051T326/7 C ...
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... C8051T622/3 and C8051T326 kHz 13 pF Figure 16.2. External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference ...
Page 95
... Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 16.6 (OSCXCN 22: 0.150 MHz = 3.0) 3 0.150 MHz 146 48.8 pF Therefore, the XFCN value to use in this example is 011b and pF. C8051T622/3 and C8051T326/7 3 ...
Page 96
... C8051T622/3 and C8051T326/7 SFR Definition 16.6. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2:0] R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and is valid at all times for all modes of opera- tion except External CMOS Clock Mode and External CMOS Clock Mode with divide by 2 ...
Page 97
... SMBus SYSCLK 4 PCA 2 T0 Lowest UART1 Priority 8 P0 (P0.0-P0. (P1.0-P1. (P2.0) Figure 17.1. Port I/O Functional Block Diagram C8051T622/3 and C8051T326/7 XBR0, XBR1, Port Match XBR2, PnSKIP P0MASK, P0MAT Registers P1MASK, P1MAT External Interrupts Priority Decoder PnMDIN Registers Digital P0 8 I/O Crossbar Cells P1 7 I/O Cells ...
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... C8051T622/3 and C8051T326/7 17.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 17.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1). ...
Page 99
... ECI), T0, T1, or UART1. have their PnSKIP bit set to 0. Note: The Crossbar will always assign UART0 pins to P0.4 and P0.5. Any pin used for GPIO Note: Port pin P1.6 is only available on C8051T622/3. devices. C8051T622/3 and C8051T326/7 Potentially Assignable Port Pins P0.2, P0.3 P0.3 Potentially Assignable Port Pins P0.0 - P2.0 Rev ...
Page 100
... External Interrupt 0 External Interrupt 1 Port Match Note: Port pin P1.6 is available only on C8051T622/3 devices. 17.3. Priority Crossbar Decoder The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud- ing UART0, which is always at pins 4 and 5) ...
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... C8051T622/3 and C8051T326 tio ...
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... C8051T622/3 and C8051T326 tio ...
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... C8051T622/3 and C8051T326 tio ...
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... C8051T622/3 and C8051T326/7 17.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT) ...
Page 105
... SPI I/O Enable. 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either GPIO pins. 0 URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. C8051T622/3 and C8051T326 SYSCKE SMB0E R R R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE Type R/W R/W Reset 0 0 SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). 1: Weak Pullups disabled. ...
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... P0MASK (P1 & P1MASK) does not equal (P1MATCH & P1MASK). A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt and wake-up sources. C8051T622/3 and C8051T326 ...
Page 108
... C8051T622/3 and C8051T326/7 SFR Definition 17.4. P0MASK: Port 0 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAE Bit Name 7:0 P0MASK[7:0] Port 0 Mask Value. Selects P0 pins to be compared to the corresponding bits in P0MAT. 0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event. ...
Page 109
... SFR. Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig- ital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their PnSKIP bit set to 1. C8051T622/3 and C8051T326 ...
Page 110
... C8051T622/3 and C8051T326/7 The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port cell can be configured for analog or digital I/O. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is P2.0, which can only be used for digital I/O ...
Page 111
... Name Type Reset 0 0 SFR Address = 0xA4 Bit Name 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. C8051T622/3 and C8051T326 P0MDIN[7:0] R Function ...
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... C8051T622/3 and C8051T326/7 SFR Definition 17.11. P0SKIP: Port 0 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. ...
Page 113
... Unused Unused/ Read = 0b. Write = don’t care. 6:0 P1MDOUT[6:0] Output Configuration Bits for P1.7–P1.0 (respectively). These bits are ignored if the corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. Note: P1.6 is not available on all devices C8051T622/3 and C8051T326 P1MDIN[6:0] R/W 1 ...
Page 114
... C8051T622/3 and C8051T326/7 SFR Definition 17.15. P1SKIP: Port 1 Skip Bit 7 6 Name Type R Reset 0 0 SFR Address = 0xD5 Bit Name 7 Unused Unused. Read = 0b. Write = don’t care. 6:0 P1SKIP[6:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar ...
Page 115
... Name Type R R Reset 0 0 SFR Address = 0xA6 Bit Name 7:1 Unused Unused. Read = 0000000b. Write = don’t care. 0 P2MDOUT[0] Output Configuration Bit for P2.0.. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. C8051T622/3 and C8051T326 Function Rev. 1 P2MDOUT[0] R R/W ...
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... C8051T622/3 and C8051T326/7 18. Universal Serial Bus Controller (USB0) C8051T622/3 and C8051T326/7 devices include a complete Full/Low Speed USB function for USB periph- eral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 256-Byte FIFO block, and clock recovery mechanism for crystal-less operation ...
Page 117
... USB0XCN can be used for Transceiver testing as described in SFR Definition 18.1. The pull-up resistor is enabled only when VBUS is present (see Section “7.1.2. VBUS Detection” on page 35 for details on VBUS detection). Important Note: The USB clock should be active before the Transceiver is enabled. C8051T622/3 and C8051T326/7 USB Protocol Address Endpoint0 IN Endpoint1 IN Endpoint2 IN Rev ...
Page 118
... C8051T622/3 and C8051T326/7 SFR Definition 18.1. USB0XCN: USB0 Transceiver Control Bit 7 6 Name PREN PHYEN SPEED Type R/W R/W Reset 0 0 SFR Address = 0xD7 Bit Name 7 PREN Internal Pull-up Resistor Enable. The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from USB network). ...
Page 119
... See the “Indexed Registers” section of Table 18.2 for a list of endpoint control/status registers. Important Note: The USB clock must be active when accessing USB registers. 8051 SFRs USB0DAT USB0ADR Figure 18.2. USB0 Register Access Scheme C8051T622/3 and C8051T326/7 USB Controller Interrupt Registers FIFO Access Common Registers ...
Page 120
... C8051T622/3 and C8051T326/7 SFR Definition 18.2. USB0ADR: USB0 Indirect Address Bit 7 6 Name BUSY AUTORD Type R/W R/W Reset 0 0 SFR Address = 0x96 Bit Name Description 7 BUSY USB0 Register Read Busy Flag. This bit is used during indirect USB0 accesses. 6 AUTORD USB0 Register Auto-read Flag. ...
Page 121
... Type Reset 0 0 SFR Address = 0x97 Bit Name Description 7:0 USB0DAT[7:0] USB0 Data Bits. This SFR is used to indi- rectly read and write USB0 registers. C8051T622/3 and C8051T326 USB0DAT[7:0] R Write Write Procedure: 1. Poll for BUSY (USB0ADR.7) => Load the target USB0 ...
Page 122
... C8051T622/3 and C8051T326/7 Table 18.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F EENABLE 0x1E FIFOn 0x20-0x22 ...
Page 123
... Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode. Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres- ent on the USB network. This mode is not required (or recommended) in typical USB environments. C8051T622/3 and C8051T326 ...
Page 124
... C8051T622/3 and C8051T326/7 USB Register Definition 18.5. CLKREC: Clock Recovery Control Bit 7 6 Name CRE CRSSEN CRLOW Type R/W R/W Reset 0 0 USB Register Address = 0x0F Bit Name 7 CRE Clock Recovery Enable Bit. This bit enables/disables the USB clock recovery feature. 0: Clock recovery disabled. ...
Page 125
... Endpoints1-2. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 18.3 for a list of maximum packet sizes for each FIFO configuration. C8051T622/3 and C8051T326/7 Configurable as IN, O UT, or both (Split ...
Page 126
... C8051T622/3 and C8051T326/7 Table 18.3. FIFO Configurations Endpoint Split Mode Number Enabled 18.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end- point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO ...
Page 127
... Writing the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to their default values following this asynchronous reset. Suspend Mode: With Suspend Detection enabled (SUSEN = 1), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = 1). The C8051T622/3 and C8051T326 ...
Page 128
... C8051T622/3 and C8051T326/7 Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section “16.3. Programmable Internal High-Frequency (H-F) Oscillator” on page 89 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. ...
Page 129
... USB0 not in suspend mode. 1: USB0 in suspend mode. 0 SUSEN Suspend Detection Enable. 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend sig- naling on the bus. C8051T622/3 and C8051T326 USBINH USBRST RESUME ...
Page 130
... C8051T622/3 and C8051T326/7 USB Register Definition 18.9. FRAMEL: USB0 Frame Number Low Bit 7 6 Name Type Reset 0 0 USB Register Address = 0x0C Bit Name 7:0 FRMEL[7:0] Frame Number Low Bits. This register contains bits 7-0 of the last received frame number. USB Register Definition 18.10. FRAMEH: USB0 Frame Number High ...
Page 131
... This bit is cleared when software reads the IN1INT register Endpoint 1 interrupt inactive Endpoint 1 interrupt active. 0 EP0 Endpoint 0 Interrupt-Pending Flag. This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. C8051T622/3 and C8051T326 ...
Page 132
... C8051T622/3 and C8051T326/7 USB Register Definition 18.12. OUT1INT: USB0 OUT Endpoint Interrupt Bit 7 6 Name Type R R Reset 0 0 USB Register Address = 0x04 Bit Name 7:3 Unused Unused. Read = 00000b. Write = don’t care. 2 OUT2 OUT Endpoint 2 Interrupt-pending Flag. This bit is cleared when software reads the OUT1INT register. ...
Page 133
... Suspend Interrupt-pending Flag. When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active. C8051T622/3 and C8051T326 SOF RSTINT ...
Page 134
... C8051T622/3 and C8051T326/7 USB Register Definition 18.14. IN1IE: USB0 IN Endpoint Interrupt Enable Bit 7 6 Name Type R R Reset 0 0 USB Register Address = 0x07 Bit Name 7:3 Unused Unused. Read = 00000b. Write = don’t care. 2 IN2E IN Endpoint 2 Interrupt Enable Endpoint 2 interrupt disabled Endpoint 2 interrupt enabled. ...
Page 135
... OUT2E OUT Endpoint 2 Interrupt Enable. 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. 1 OUT1E OUT Endpoint 1 Interrupt Enable. 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. 0 Unused Unused. Read = 0b. Write = don’t care. C8051T622/3 and C8051T326 OUT2E R Function Rev ...
Page 136
... C8051T622/3 and C8051T326/7 USB Register Definition 18.16. CMIE: USB0 Common Interrupt Enable Bit 7 6 Name Type R R Reset 0 0 USB Register Address = 0x0B Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 SOFE Start of Frame Interrupt Enable. 0: SOF interrupt disabled. 1: SOF interrupt enabled. ...
Page 137
... Firmware sends a packet less than the maximum Endpoint0 packet size. 3. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR. when performing (2) and (3) above. The SIE will transmit a NAK in response token if there is no packet ready in the IN FIFO (INPRDY = 0). C8051T622/3 and C8051T326/7 Rev. 1.1 137 ...
Page 138
... C8051T622/3 and C8051T326/7 18.10.3. Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR. and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR ...
Page 139
... SETUP packet. 3) The packet is overwritten by an incoming OUT packet. 0 OPRDY OUT Packet Ready Bit. Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes 1 to the SOPRDY bit. C8051T622/3 and C8051T326 SUEND DATAEND ...
Page 140
... C8051T622/3 and C8051T326/7 USB Register Definition 18.18. E0CNT: USB0 Endpoint0 Data Count Bit 7 6 Name Type R Reset 0 0 USB Register Address = 0x16 Bit Name 7 Unused Unused. Read = 0b. Write = don’t care. 6:0 E0CNT[6:0] Endpoint 0 Data Count. This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO ...
Page 141
... A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener- ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The STSTL bit must be reset firmware. C8051T622/3 and C8051T326 ...
Page 142
... C8051T622/3 and C8051T326/7 Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY interrupt will not be generated in this case ...
Page 143
... Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot the endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the next SOF is received. Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. C8051T622/3 and C8051T326 SDSTL ...
Page 144
... C8051T622/3 and C8051T326/7 USB Register Definition 18.21. EINCSRH: USB0 IN Endpoint Control High Bit 7 6 Name DBIEN ISO DIRSEL Type R/W R/W Reset 0 0 USB Register Address = 0x12 Bit Name 7 DBIEN IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. ...
Page 145
... FIFO, OPRDY will be set interrupt (if enabled) will be gen- erated, and the DATAERR bit (EOUTCSRL.3) will be set to 1. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. C8051T622/3 and C8051T326/7 Rev. 1.1 145 ...
Page 146
... C8051T622/3 and C8051T326/7 USB Register Definition 18.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Bit 7 6 Name CLRDT STSTL Type W R/W Reset 0 0 USB Register Address = 0x14 Bit Name Description 7 CLRDT Clear Data Toggle Bit. Software should write STSTL Sent Stall Bit. ...
Page 147
... USB Register Address = 0x16 Bit Name 7:0 EOCL[7:0] OUT Endpoint Count Low Byte. EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1. C8051T622/3 and C8051T326 ...
Page 148
... C8051T622/3 and C8051T326/7 USB Register Definition 18.25. EOUTCNTH: USB0 OUT Endpoint Count High Bit 7 6 Name Type R R Reset 0 0 USB Register Address = 0x17 Bit Name 7:2 Unused Unused. Read = 000000b. Write = don’t care. 1:0 EOCH[1:0] OUT Endpoint Count High Byte. EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO ...
Page 149
... SMB0ADR SMB0ADM Figure 19.1. SMBus Block Diagram C8051T622/3 and C8051T326 serial bus. Reads and writes ...
Page 150
... C8051T622/3 and C8051T326/7 19.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
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... When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to C8051T622/3 and C8051T326/7 R/W D7 ...
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... C8051T622/3 and C8051T326/7 overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 19.3.5. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free ...
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... SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times C8051T622/3 and C8051T326/7 SMBCS0 SMBus Clock Source ...
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... C8051T622/3 and C8051T326/7 meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 19.2 shows the min- imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Table 19.2. Minimum SDA Setup and Hold Times ...
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... These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 19.1. 00: Timer 0 Overflow 01: Timer 1 Overflow 10: Timer 2 High Byte Overflow 11: Timer 2 Low Byte Overflow C8051T622/3 and C8051T326 EXTHOLD SMBTOE SMBFTE ...
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... C8051T622/3 and C8051T326/7 19.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 19.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER indicates whether a device is the master or slave during the current transfer ...
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... ARBLOST SMBus Arbitration Lost Indicator. 1 ACK SMBus Acknowledge SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 15.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. C8051T622/3 and C8051T326 STA STO ACKRQ ARBLOST R/W R ...
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... C8051T622/3 and C8051T326/7 Table 19.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed by an address byte is STA received. A STOP is detected while addressed as a slave ...
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... General Call Address Enable. When hardware address recognition is enabled (EHACK = 1), this bit will deter- mine whether the General Call Address (0x00) is also recognized by hardware. 0: General Call Address is ignored. 1: General Call Address is recognized. C8051T622/3 and C8051T326/7 GC bit Slave Addresses Recognized by Hardware 0 0x34 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 19.4. SMB0ADM: SMBus Slave Address Mask Bit 7 6 Name Type Reset 1 1 SFR Address = 0xCF Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored. Any bit set SLVM[6:0] enables compari- sons with the corresponding bit in SLV[6:0] ...
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... The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 19.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP ...
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... ACK when hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA R Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface Figure 19.6. Typical Master Read Sequence C8051T622/3 and C8051T326/7 A Data Byte A Data Byte S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Rev ...
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... C8051T622/3 and C8051T326/7 19.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc- tion bit (WRITE in this case) is received ...
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... SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ- ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi- cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification. C8051T622/3 and C8051T326/7 Interrupts with Hardware ACK Enabled (EHACK = 1) A ...
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... C8051T622/3 and C8051T326/7 Table 19.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte was transmitted; ACK received ...
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... Lost arbitration while attempt ing a STOP. A slave byte was received; 0000 ACK requested. C8051T622/3 and C8051T326/7 (Continued) Typical Response Options No action required (expecting STOP condition). Load SMB0DAT with next data byte to transmit. No action required (expecting Master to end transfer). ...
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... C8051T622/3 and C8051T326/7 Table 19.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values Read Current SMbus State Lost arbitration while attempt- 0010 ing a repeated START. Lost arbitration due to a 0001 detected STOP. Lost arbitration while transmit- 0000 ting a data byte as master ...
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... X error detected. An illegal STOP or bus error 0101 was detected while a Slave Transmission was in progress. C8051T622/3 and C8051T326/7 (Continued) Typical Response Options Set ACK for next data byte; Read SMB0DAT. Set NACK to indicate next data byte as the last data byte; ...
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... C8051T622/3 and C8051T326/7 Table 19.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) Values Read Current SMbus State A slave address + R/W was received; ACK sent. 0010 Lost arbitration as master slave address + R/W received; ACK sent. A STOP was detected while addressed as a Slave Trans- mitter or Slave Receiver ...
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... CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Write to SBUF UART Baud Rate Generator Figure 20.1. UART0 Block Diagram C8051T622/3 and C8051T326/7 SFR Bus TB8 SBUF SET (TX Shift ...
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... C8051T622/3 and C8051T326/7 20.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 20.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
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... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 20.4. 8-Bit UART Timing Diagram C8051T622/3 and C8051T326/7 TX RS-232 RS-232 C8051xxxx LEVEL RX XLTR ...
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... C8051T622/3 and C8051T326/7 20.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
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... Master Slave Device Device Figure 20.6. UART Multi-Processor Mode Interconnect Diagram C8051T622/3 and C8051T326/7 Slave Slave Device Device Rev. 1.1 V+ ...
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... C8051T622/3 and C8051T326/7 SFR Definition 20.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. ...
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... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 Table 20.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’ ...
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... The internal timer counts up from the reload value on every clock tick. On timer overflows (0xFFFF to 0x0000), the timer is reloaded. For reliable UART operation recommended that the UART baud rate is not configured for baud rates faster than SYSCLK/16. The baud rate for UART1 is defined in Equation 21.1. C8051T622/3 and C8051T326/7 Data Formatting SMOD1 Control / Status ...
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... C8051T622/3 and C8051T326/7 Baud Rate = Equation 21.1. UART1 Baud Rate A quick reference for typical baud rates and system clock frequencies is given in Table 21.1. Table 21.1. Baud Rate Generator Settings for Standard Baud Rates Target Baud Actual Baud Rate (bps) Rate (bps) 230400 230769 115200 ...
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... In both types of applications, data is transmitted from the microcontroller on the TX1 pin, and received on the RX1 pin. The TX1 and RX1 pins are configured using the crossbar and the Port I/O registers, as detailed in Section “17. Port Input/Output” on page 97. C8051T622/3 and C8051T326 ...
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... C8051T622/3 and C8051T326/7 In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX) input of the other device, either directly or through a bus transceiver, as shown in Figure 21.5. PC COM Port Figure 21.5. Typical UART Interconnect Diagram 21.3.1. Data Transmission Data transmission is double-buffered, and begins when software writes a data byte to the SBUF1 register. ...
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... Master Slave Device Device Figure 21.6. UART Multi-Processor Mode Interconnect Diagram C8051T622/3 and C8051T326/7 Slave Device Device Rev. 1.1 Slave V+ ...
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... C8051T622/3 and C8051T326/7 SFR Definition 21.1. SCON1: UART1 Control Bit 7 6 Name OVR1 PERR1 Type R/W R/W Reset 0 0 SFR Address = 0xD2 Bit Name 7 OVR1 Receive FIFO Overrun Flag. This bit indicates a receive FIFO overrun condition, where an incoming character is discarded due to a full FIFO. This bit must be cleared software. ...
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... Extra Bit Disabled. 1: Extra Bit Enabled. 0 SBL1 Stop Bit Length. 0: Short—Stop bit is active for one bit time. 1: Long—Stop bit is active for two bit times (data length = bits), or 1.5 bit times (data length = 5 bits). C8051T622/3 and C8051T326 PE1 S1DL[1:0] R/W R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 21.3. SBUF1: UART1 Data Buffer Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD3 Bit Name Description 7:0 SBUF1[7:0] Serial Data Buffer Bits. This SFR is used to both send data from the UART and to read received data from the UART1 receive FIFO ...
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... SFR Definition 21.5. SBRLH1: UART1 Baud Rate Generator High Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0xB5 Bit Name 7:0 SBRLH1[7:0] UART1 Baud Rate Reload High Bits. High Byte of reload value for UART1 Baud Rate Generator. C8051T622/3 and C8051T326 Reserved Reserved Reserved R/W R/W R Function ...
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... C8051T622/3 and C8051T326/7 SFR Definition 21.6. SBRLL1: UART1 Baud Rate Generator Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0xB4 Bit Name 7:0 SBRLL1[7:0] UART1 Baud Rate Reload Low Bits. Low Byte of reload value for UART1 Baud Rate Generator. 188 ...
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... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 22.1. SPI Block Diagram C8051T622/3 and C8051T326/7 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
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... C8051T622/3 and C8051T326/7 22.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 22.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
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... I/O pins. Figure 22.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. Master Device 1 Figure 22.2. Multiple-Master Mode Connection Diagram Master Device Figure 22.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram C8051T622/3 and C8051T326/7 NSS GPIO MISO MISO Master MOSI MOSI ...
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... C8051T622/3 and C8051T326/7 Master Device GPIO Figure 22.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 22.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal ...
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... SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. C8051T622/3 and C8051T326/7 Rev. 1.1 193 ...
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... C8051T622/3 and C8051T326/7 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 22.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 22 ...
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... SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. C8051T622/3 and C8051T326/7 Bit 6 Bit 5 Bit 4 ...
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... C8051T622/3 and C8051T326/7 SFR Definition 22.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). 6 MSTEN Master Mode Enable. ...
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... This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 SPIEN SPI0 Enable. 0: SPI disabled. 1: SPI enabled. C8051T622/3 and C8051T326 RXOVRN NSSMD[1:0] R/W R/W ...
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... C8051T622/3 and C8051T326/7 SFR Definition 22.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided ver- ...
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... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 22.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 22.9. SPI Master Timing (CKPHA = 1) C8051T622/3 and C8051T326/7 T MCKL T T MIS MIH T MCKL T MIH Rev ...
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... C8051T622/3 and C8051T326/7 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 22.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...