C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 8

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
List of Figures
8
Figure 1.1. C8051T622/3 and C8051T326/7 Block Diagram .................................. 16
Figure 1.2. Typical Bus-Powered Connections for the C8051T622/3 and 
Figure 1.3. Typical Bus-Powered Connections for the C8051T327 ........................ 17
Figure 3.1. C8051T622/3 (QFN-24) Pinout Diagram (Top View) ............................ 21
Figure 3.2. C8051T326 (QFN-28) Pinout Diagram (Top View) ............................... 22
Figure 3.3. C8051T327 (QFN-28) Pinout Diagram (Top View) ............................... 23
Figure 4.1. QFN-24 Package Drawing .................................................................... 24
Figure 4.2. QFN-24 Recommended PCB Land Pattern .......................................... 25
Figure 5.1. QFN-28 Package Drawing .................................................................... 26
Figure 5.2. QFN-28 Recommended PCB Land Pattern .......................................... 27
Figure 6.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 34
Figure 6.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 34
Figure 7.1. REG0 Configuration: USB Bus-Powered .............................................. 35
Figure 7.2. REG0 Configuration: USB Self-Powered .............................................. 36
Figure 7.3. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 36
Figure 7.4. REG0 Configuration: No USB Connection ............................................ 37
Figure 8.1. CIP-51 Block Diagram ........................................................................... 40
Figure 10.1. Memory Map ....................................................................................... 50
Figure 10.2. Program Memory Map ......................................................................... 51
Figure 10.3. USB FIFO Space and XRAM Memory Map with USBFAE set to 1 ..... 54
Figure 15.1. Reset Sources ..................................................................................... 80
Figure 15.2. Power-On and VDD Monitor Reset Timing ......................................... 81
Figure 16.1. Oscillator Options ................................................................................ 86
Figure 16.2. External Crystal Example .................................................................... 94
Figure 17.1. Port I/O Functional Block Diagram ...................................................... 97
Figure 17.2. Port I/O Cell Block Diagram ................................................................ 98
Figure 17.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 101
Figure 17.4. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 102
Figure 17.5. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 103
Figure 18.1. USB0 Block Diagram ......................................................................... 116
Figure 18.2. USB0 Register Access Scheme ........................................................ 119
Figure 18.3. USB FIFO Allocation ......................................................................... 125
Figure 19.1. SMBus Block Diagram ...................................................................... 149
Figure 19.2. Typical SMBus Configuration ............................................................ 150
Figure 19.3. SMBus Transaction ........................................................................... 151
Figure 19.4. Typical SMBus SCL Generation ........................................................ 153
Figure 19.5. Typical Master Write Sequence ........................................................ 162
Figure 19.6. Typical Master Read Sequence ........................................................ 163
Figure 19.7. Typical Slave Write Sequence .......................................................... 164
Figure 19.8. Typical Slave Read Sequence .......................................................... 165
Figure 20.1. UART0 Block Diagram ...................................................................... 171
Figure 20.2. UART0 Baud Rate Logic ................................................................... 172
C8051T326 ........................................................................................... 17
Rev. 1.1