C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 98

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
17.1. Port I/O Modes of Operation
Port pins use the Port I/O cell shown in Figure 17.2. Each Port I/O cell can be configured by software for
analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance
state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1).
17.1.1. Port Pins Configured for Analog I/O
Any pins to be used as an external oscillator input/output should be configured for analog I/O (PnMDIN.n =
1). When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled.
Port pins configured for analog I/O will always read back a value of 0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
17.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the V
logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive
the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high and
low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the V
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
98
WEAKPUD
(Weak Pull-Up Disable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
DD
supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
PxMDIN.x
(1 for digital)
(0 for analog)
Figure 17.2. Port I/O Cell Block Diagram
Rev. 1.1
IO
or GND supply rails based on the output
VIO
GND
VIO
(WEAK)
PORT
PAD