C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 56

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051T622/3 and C8051T326/7's
resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 imple-
mentation as well as implementing additional SFRs used to configure and access the sub-systems unique
to the C8051T622/3 and C8051T326/7. This allows the addition of new functionality while retaining com-
patibility with the MCS-51™ instruction set. Table 11.1 lists the SFRs implemented in the C8051T622/3
and C8051T326/7 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.2, for a detailed description of each register.
56
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
E8
E0
D8 PCA0CN
D0
C8 TMR2CN REG01CN TMR2RLL TMR2RLH
C0 SMB0CN
B8
B0
A8
A0
F8 SPI0CN
F0
98
90
88
80
SCON0
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
-
-
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
SMB0CF
CLKMUL
TMR3CN
CLKSEL
P0MDIN
SBUF0
PCA0L
TMOD
XBR0
1(9)
Table 11.1. Special Function Register (SFR) Memory Map
SP
-
SMB0DAT
TMR3RLL TMR3RLH
SPI0CKR
P1MASK
OSCICN
P1MDIN
EMI0CN
SCON1
PCA0H
XBR1
DPL
2(A)
TL0
—
PCA0CPL0 PCA0CPH0
SPI0DAT
OSCICL
SBUF1
XBR2
DPH
3(B)
TL1
—
—
—
—
-
Rev. 1.1
PCA0PWM
P0MDOUT P1MDOUT P2MDOUT
SBCON1
SBRLL1
P0SKIP
IT01CF
TMR2L
TMR3L
P0MAT
TH0
4(C)
—
—
—
SBRLH1
EMI0CF
SMOD1
P1SKIP
TMR2H
TMR3H
IAPCN
5(D)
TH1
—
—
—
—
—
—
-
USB0ADR
OSCLCN
P0MASK
CKCON
P1MAT
EIP1
EIE1
6(E)
—
—
—
—
—
—
—
—
SMB0ADM
SMB0ADR
USB0XCN
USB0DAT
MEMKEY
VDM0CN
RSTSRC
PFE0CN
PSCTL
PCON
EIP2
EIE2
7(F)
—
—
—
—