C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 141

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

USB Register Definition 18.19. EENABLE: USB0 Endpoint Enable
USB Register Address = 0x1E
18.12. Controlling Endpoints1-2 IN
Endpoints1-2 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-2 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes 1 to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
18.12.1. Endpoints1-2 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt Mode. Once an end-
point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0
SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the
INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the
INPRDY bit, and generate an interrupt.
Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While
SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener-
ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The
STSTL bit must be reset to 0 by firmware.
Name
Reset
Bit
7:3
Type
2
1
0
Bit
Reserved
Unused
Name
EEN2
EEN1
R
7
1
Unused. Read = 11111b. Write = don’t care.
Endpoint 2 Enable.
This bit enables/disables Endpoint 2.
0: Endpoint 2 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 2 is enabled (normal).
Endpoint 1 Enable.
This bit enables/disables Endpoint 1.
0: Endpoint 1 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 1 is enabled (normal).
Reserved. Read = 1b. Must Write 1b.
R
6
1
R
5
1
C8051T622/3 and C8051T326/7
Rev. 1.1
R
4
1
Function
R
3
1
EEN2
R/W
2
1
EEN1
R/W
1
1
Reserved
R/W
0
1
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