C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 5

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

19. SMBus................................................................................................................... 149
18.1. Endpoint Addressing ..................................................................................... 116
18.2. USB Transceiver ........................................................................................... 117
18.3. USB Register Access .................................................................................... 119
18.4. USB Clock Configuration............................................................................... 123
18.5. FIFO Management ........................................................................................ 124
18.6. Function Addressing...................................................................................... 127
18.7. Function Configuration and Control............................................................... 127
18.8. Interrupts ....................................................................................................... 130
18.9. The Serial Interface Engine ........................................................................... 136
18.10. Endpoint0 .................................................................................................... 136
18.11. Configuring Endpoints1-2 ............................................................................ 140
18.12. Controlling Endpoints1-2 IN......................................................................... 141
18.13. Controlling Endpoints1-2 OUT..................................................................... 144
19.1. Supporting Documents .................................................................................. 150
19.2. SMBus Configuration..................................................................................... 150
19.3. SMBus Operation .......................................................................................... 150
19.4. Using the SMBus........................................................................................... 152
19.5. SMBus Transfer Modes................................................................................. 162
19.6. SMBus Status Decoding................................................................................ 165
18.5.1. FIFO Split Mode .................................................................................... 125
18.5.2. FIFO Double Buffering .......................................................................... 125
18.5.1. FIFO Access ......................................................................................... 126
18.10.1. Endpoint0 SETUP Transactions ......................................................... 137
18.10.2. Endpoint0 IN Transactions.................................................................. 137
18.10.3. Endpoint0 OUT Transactions.............................................................. 138
18.12.1. Endpoints1-2 IN Interrupt or Bulk Mode.............................................. 141
18.12.2. Endpoints1-2 IN Isochronous Mode.................................................... 142
18.13.1. Endpoints1-2 OUT Interrupt or Bulk Mode.......................................... 145
18.13.2. Endpoints1-2 OUT Isochronous Mode................................................ 145
19.3.1. Transmitter Vs. Receiver....................................................................... 151
19.3.2. Arbitration.............................................................................................. 151
19.3.3. Clock Low Extension............................................................................. 151
19.3.4. SCL Low Timeout.................................................................................. 151
19.3.5. SCL High (SMBus Free) Timeout ......................................................... 152
19.4.1. SMBus Configuration Register.............................................................. 152
19.4.2. SMB0CN Control Register .................................................................... 156
19.4.3. Hardware Slave Address Recognition .................................................. 158
19.4.4. Data Register ........................................................................................ 161
19.5.1. Write Sequence (Master) ...................................................................... 162
19.5.2. Read Sequence (Master) ...................................................................... 163
19.5.3. Write Sequence (Slave) ........................................................................ 164
19.5.4. Read Sequence (Slave) ........................................................................ 165
19.4.2.1. Software ACK Generation ............................................................ 156
19.4.2.2. Hardware ACK Generation ........................................................... 156
C8051T622/3 and C8051T326/7
Rev. 1.1
5