C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 238

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C8051T622-GMR

Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051T622-GMR

Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051

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Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T622-GMR
Manufacturer:
SILICON
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5 000
C8051T622/3 and C8051T326/7
SFR Definition 24.1. PCA0CN: PCA Control
SFR Address = 0xD8; Bit-Addressable
238
Name
Reset
5:3
Bit
Type
7
6
2
1
0
Bit
Unused
Name
CCF2
CCF1
CCF0
CF
CR
R/W
CF
7
0
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Unused. Read = 000b, Write = Don't care.
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
R/W
CR
6
0
R
5
0
Rev. 1.1
R
4
0
Function
R
3
0
CCF2
R/W
2
0
CCF1
R/W
1
0
CCF0
R/W
0
0

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