C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 143

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

USB Register Definition 18.20. EINCSRL: USB0 IN Endpoint Control Low
USB Register Address = 0x11
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
UNDRUN Data Underrun Bit.
INPRDY In Packet Ready.
FIFONE FIFO Not Empty.
Unused
CLRDT
SDSTL
FLUSH
STSTL
Name
R
7
0
Unused. Read = 0b. Write = don’t care.
Clear Data Toggle Bit. Software should write 1 to
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. The FIFO is
flushed, and the INPRDY bit cleared. This flag must be cleared by software.
Send Stall.
Software should write 1 to this bit to generate a STALL handshake in response to an IN
token. Software should write 0 to this bit to terminate the STALL signal. This bit has no
effect in ISO mode.
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint
FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains mul-
tiple packets, software must write 1 to FLUSH for each packet. Hardware resets the
FLUSH bit to 0 when the FIFO flush is complete.
The function of this bit depends on the IN Endpoint mode:
ISO: Set when a zero-length packet is sent after an IN token is received while bit
INPRDY = 0.
Interrupt/Bulk: Set when a NAK is returned in response to an IN token.
This bit must be cleared by software.
0: The IN Endpoint FIFO is empty.
1. The IN Endpoint FIFO contains one or more packets.
Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO.
Hardware clears INPRDY due to any of the following: 1) A data packet is transmitted. 2)
Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot. 3) If the
endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the
next SOF is received.
Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a
CLRDT
Description
packet being transmitted.
W
6
0
STSTL
R/W
5
0
C8051T622/3 and C8051T326/7
this bit to reset the IN End-
point data toggle to 0.
SDSTL
R/W
Rev. 1.1
4
0
Write
FLUSH
R/W
3
0
UNDRUN
R/W
This bit always reads 0.
2
0
FIFONE
R/W
Read
1
0
INPRDY
R/W
0
0
143