C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 153

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 19.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “23. Timers” on page 202.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 19.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 19.2.
Figure 19.4 shows the typical SCL generation described by Equation 19.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 19.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
Timer Source
Overflows
SCL
LOW
Equation 19.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
T
Low
SMBCS1
T
Figure 19.4. Typical SMBus SCL Generation
Table 19.1. SMBus Clock Source Selection
HighMin
0
0
1
1
Equation 19.2. Typical SMBus Bit Rate
BitRate
SMBCS0
=
T
High
C8051T622/3 and C8051T326/7
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.1
Timer 2 High Byte Overflow
=
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
HIGH
is typically
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