C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 97

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

17. Port Input/Output
Digital and analog resources are available through 16 or 15 I/O pins, depending on the specific device.
Port pins P0.0-P1.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 17.3. Port pin P2.0 on can be used as
GPIO and is shared with the C2 Interface Data signal (C2D). The designer has complete control over
which functions are assigned, limited only by the number of physical I/O pins. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin
can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 17.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 17.1, SFR Definition 17.2,
and SFR Definition 17.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 17.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 6.3 on page 30
Highest
Priority
Lowest
Priority
SYSCLK
UART0
SMBus
UART1
T0, T1
P0 (P0.0-P0.7)
P1
P2
PCA
SPI
Figure 17.1. Port I/O Functional Block Diagram
(P1.0-P1.6)
(P2.0)
2
4
2
4
2
2
8
7
1
C8051T622/3 and C8051T326/7
Rev. 1.1
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
Digital
1
Note: Not available on C8051T326/7 devices.
8
7
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cell
P0
I/O
P1
I/O
P2
I/O
External Interrupts
PnMDIN Registers
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.6
P2.0
1
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