C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 53

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block bound-
ary.
SFR Definition 10.1. EMI0CN: External Memory Interface Control
SFR Address = 0xAA
10.2.3. Accessing USB FIFO Space
The C8051T622/3 and C8051T326/7 include 256 bytes of RAM which functions as USB FIFO space.
Figure 10.3 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally
accessed via USB FIFO registers; see Section “18.5. FIFO Management” on page 124 for more informa-
tion on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in
the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to '1', and (2) the USB clock frequency must be greater than or
equal to twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped
into XRAM space at addresses 0x0400 to 0x04FF. The normal on-chip XRAM at the same addresses can-
not be accessed when the USBFAE bit is set to 1.
Important Note: The USB clock must be active when accessing FIFO space.
Name
Reset
Bit
7:3
2:0 PGSEL[2:0] XRAM Page Select.
Type
Bit
UNUSED
Name
R
7
0
Unused. Read = 00000b; Write = Don’t Care
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be
accessed.
R
6
0
R
5
0
C8051T622/3 and C8051T326/7
Rev. 1.1
R
4
0
Function
R
3
0
R/W
2
0
PGSEL[2:0]
R/W
1
0
R/W
0
0
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