C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 81

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

15.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on or V
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
is enabled following a power-on reset.
Logic HIGH
RST
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
ramp time is defined as how fast V
RST
monitor event timing. The maximum V
Figure 15.2. Power-On and V
V
RST
DD
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
Power-On
PORDelay
Reset
C8051T622/3 and C8051T326/7
T
) is typically less than 0.3 ms.
PORDelay
Rev. 1.1
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
RST
Monitor
Reset
VDD
level. For ramp times less than
RST
). Figure 15.2. plots the
DD
settles above
DD
VDD
DD
ramp time
monitor
t
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