MA240029 Microchip Technology, MA240029 Datasheet - Page 302

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
REGISTER 24-2:
DS39996F-page 302
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
Note 1:
PVCFG1
BUFS
R/W-0
R/W-0
(1)
These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
1x = Unimplemented, do not use
01 = External V
00 = AV
NVCFG0: Converter Negative Voltage Reference Configuration bits
1 = External V
0 = AV
OFFCAL: Offset Calibration Mode Select bit
1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AV
0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
1 = A/D is filling the upper half of the buffer; user should access data in the lower half
0 = A/D is filling the lower half of the buffer; user should access data in the upper half
SMPI<4:0>: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1:
0001 = For 2-channel DMA A/D operation
0000 = For 1-channel DMA A/D operation
When DMAEN = 0:
Selects the number of sample/conversions per each interrupt
11111 = Interrupt/address increment at the completion of conversion for each 32nd sample
11110 = Interrupt/address increment at the completion of conversion for each 31st sample

00001 = Interrupt/address increment at the completion of conversion for every other sample
00000 = Interrupt/address increment at the completion of conversion for each sample
PVCFG0
SMPI4
R/W-0
R/W-0
AD1CON2: A/D CONTROL REGISTER 2
SS
DD
W = Writable bit
‘1’ = Bit is set
REF
REF
NVCFG0
SMPI3
R/W-0
R/W-0
-
+
(1)
OFFCAL
SMPI2
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BUFREGEN
SMPI1
R/W-0
R/W-0
CSCNA
SMPI0
R/W-0
R/W-0
 2010-2011 Microchip Technology Inc.
x = Bit is unknown
BUFM
R/W-0
U-0
—
(1)
SS
R/W-0
ALTS
U-0
—
bit 8
bit 0