MA240029 Microchip Technology, MA240029 Datasheet - Page 94

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
TABLE 7-3:
7.4.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
DS39996F-page 94
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
7:
8:
T
T
WDTWIN<1:0> bits setting).
T
T
the oscillator clock to the system.
T
T
If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just T
primary oscillator after its respective clock delay.
T
oscillator clock to the system.
POR AND LONG OSCILLATOR
START-UP TIMES
STARTUP
OST
OST
POR
RST
LOCK
FRC
= Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
= Internal State Reset time (2 s nominal).
and T
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= PLL lock time.
= T
LPRC
VREG
Clock Source
= RC oscillator start-up times.
(10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
FRC
, and in such cases, FRC start-up time is valid. It switches to the
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
T
T
T
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.4.2
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
 2010-2011 Microchip Technology Inc.
System Clock
T
T
T
T
OST
FRC
OST
FRC
Delay
T
T
T
T
T
T
T
T
LOCK
LPRC
LOCK
LPRC
+ T
+ T
OST
+ T
OST
+ T
—
FRC
—
FRC
—
—
—
—
—
—
LOCK
LOCK
LOCK
LOCK
1, 2,
1, 2, 3,
1, 2, 3, 4,
1, 2, 3, 4, 5,
1, 2, 3, 6,
1, 2, 3, 5,
1, 2, 3,
2,
2, 3,
2, 3, 4,
2, 3, 4, 5,
2, 3, 6,
2, 3, 5,
2, 3,
3
3
3
3
3
3
3
3
5
6
Notes
5
6
8
7
6
8
7
6
8
8