MA240029 Microchip Technology, MA240029 Datasheet - Page 69

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

4.3
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
• Remapping a portion of the program space into
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word of the program word.
TABLE 4-37:
 2010-2011 Microchip Technology Inc.
Instruction Access
(Code Execution)
TBLRD/TBLWT
(Byte/Word Read/Write)
Program Space Visibility
(Block Remap/Read)
Note 1:
or words anywhere in the program space
the data space (program space visibility)
Access Type
2:
Interfacing Program and Data
Memory Spaces
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is DSRPAG<0>.
program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher
word is read.
DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of
PROGRAM SPACE ADDRESS CONSTRUCTION
User
User
Configuration
User
Access
Space
PIC24FJ128GA310 FAMILY
<23>
0
0
0
TBLPAG<7:0>
TBLPAG<7:0>
0xxx xxxx
1xxx xxxx
4.3.1
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the MSBs of TBLPAG is used to
determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
For remapping operations, the 10-bit Extended Data
Space Read register (DSRPAG) is used to define a
16K word page in the program space. When the Most
Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9)
of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are con-
catenated with the lower 15 bits of the EA to form a
23-bit program space address. The DSRPAG<8> bit
decides whether the lower word (when bit is ‘0’) or the
higher word (when bit is ‘1’) of program memory is
mapped. Unlike table operations, this strictly limits
remapping operations to the user memory area.
Table 4-37
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
0xx xxxx xxxx xxxx xxxx xxx0
<22:16>
DSRPAG<7:0>
xxxx xxxx
Program Space Address
and
ADDRESSING PROGRAM SPACE
PC<22:1>
Figure 4-8
(2)
<15>
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
show how the program EA is
Data EA<15:0>
Data EA<15:0>
xxx xxxx xxxx xxxx
<14:1>
Data EA<14:0>
DS39996F-page 69
(1)
<0>
0