MA240029 Microchip Technology, MA240029 Datasheet - Page 80

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
REGISTER 5-2:
DS39996F-page 80
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5-4
bit 3-2
bit 1
bit 0
Note 1:
SAMODE1
R/W-0
U-0
—
2:
3:
Only the original DMACNT is required to be stored to recover the original DMASRC and DMADST.
DMASRC, DMADST and DMACNT are always reloaded in Repeated mode transfers (DMACHn<2> = 1),
regardless of the state of the RELOAD bit.
The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
1 = A dummy write is initiated to DMASRC for every write to DMADST
0 = No dummy write is initiated
RELOAD: Address and Count Reload bit
1 = DMASRC, DMADST, and DMACNT registers are reloaded to their previous values upon the start
0 = DMASRC, DMADST and DMACNT are not reloaded on the start of the next operation
CHREQ: DMA Channel Software Request bit
1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending
SAMODE<1:0>: Source Address Mode Selection bits
11 = DMASRC is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRC is decremented based on SIZE bit after a transfer completion
01 = DMASRC is incremented based on SIZE bit after a transfer completion
00 = DMASRC remains unchanged after a transfer completion
DAMODE<1:0>: Destination Address Mode Selection bits
11 = DMADST is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADST is decremented based on SIZE bit after a transfer completion
01 = DMADST is incremented based on SIZE bit after a transfer completion
00 = DMADST remains unchanged after a transfer completion
TRMODE<1:0>: Transfer Mode Selection bits
11 = Repeated Continuous
10 = Continuous
01 = Repeated One-Shot
00 = One-Shot
SIZE: Data Size Selection bit
1 = Byte (8-bit)
0 = Word (16-bit)
CHEN: DMA Channel Enable bit
1 = The corresponding channel is enabled
0 = The corresponding channel is disabled
SAMODE0
R/W-0
of the next operation
U-0
—
DMACHn: DMA CHANNEL n CONTROL REGISTER
W = Writable bit
r = Reserved bit
‘1’ = Bit is set
DAMODE1
R/W-0
U-0
—
DAMODE0
R/W-0
r-0
r
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRMODE1
(3)
R/W-0
R/W-0
—
TRMODE0
NULLW
R/W-0
R/W-0
 2010-2011 Microchip Technology Inc.
x = Bit is unknown
RELOAD
R/W-0
R/W-0
SIZE
(1)
CHREQ
(2)
R/W-0
R/W-0
CHEN
bit 8
bit 0
(3)