MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 116

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 57: READ Latency (AL = 5, CL = 6)
Mode Register 2 (MR2)
Figure 58: Mode Register 2 (MR2) Definition
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
Notes:
READ n
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL),
AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC
ODT (R
is programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register will
not alter the contents of the memory array, provided it is performed correctly. The MR2
register must be loaded when all banks are idle and no data bursts are in progress, and
the controller must wait the specified time
quent operation.
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.”
T1
t RCD (MIN)
M15
0
0
1
1
M14
TT
0
1
0
1
_
WR
M10
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
0
1
1
AL = 5
NOP
). These functions are controlled via the bits shown in Figure 58. The MR2
T2
Mode Register
M9
0
1
0
1
R
Dynamic ODT
TT
_
( R
Reserved
WR
RZQ/4
RZQ/2
TT
RL = AL + CL = 11
0 1
BA2
16
disabled
_
WR
)
15
1
NOP
BA1
T6
116
0
14
BA0
0 1
13
M7
A13
0
1
0 1
12
Self Refresh Temperature
A12 A11
Extended (0°C to 95°C)
M6
Normal (0°C to 85°C)
0
1
CL = 6
0 1
11
Enabled: Automatic
Disabled: Manual
Auto Self Refresh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
R
T11
NOP
10
TT
A10
(Optional)
_
WR
t
MRD and
9
A9
0 1
Indicates A Break in
Time Scale
8
A8
1Gb: x4, x8, x16 DDR3 SDRAM
SRT
7
A7 A6 A5 A4 A3
ASR
6
NOP
T12
t
M5
MOD before initiating a subse-
0
0
0
0
1
1
1
1
5
CWL
M4
0
0
1
1
0
0
1
1
DO
4
n
M3
0
1
0
1
0
1
0
1
3
6 CK (2.5ns > t CK ≥ 1.875ns)
7 CK (1.875ns > t CK ≥ 1.5ns)
©2006 Micron Technology, Inc. All rights reserved.
0 1 0 1 0 1
8 CK (1.5ns > t CK ≥ 1.25ns)
Transitioning Data
2
CAS Write Latency (CWL)
n + 1
A2 A1 A0
DO
5 CK ( t CK ≥ 2.5ns)
1
NOP
T13
Reserved
Reserved
Reserved
Reserved
0
n + 2
DO
Address bus
Mode register 2 (MR2)
Operations
n + 3
DO
Don’t Care
NOP
T14