MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 76

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
34. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
35. The start of the write recovery time is defined as follows:
36. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
37. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How-
38. Although CKE is allowed to be registered LOW after a REFRESH command when
39. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins
40. Half-clock output parameters must be derated by the actual
41. ODT turn-off time minimum is when the device starts to turn off ODT resistance.
42. Pulse width of a input signal is defined as the width between the first crossing of
– For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
– For BC4 (OTF): Rising clock edge four clock cycles after WL
– For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in
excessive current, depending on bus activity.
ever, nine REFRESH commands must be asserted at least once every 70.3µs.
t
t
to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The
ODT reference load is shown in Figure 24 on page 49.
when input clock jitter is present. This results in each parameter becoming larger. The
parameters
ing both
t
t
ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer-
ence load is shown in Figure 25 on page 51. This output load is used for ODT timings
(see Figure 32 on page 60).
V
REFPDEN (MIN) is satisfied, there are cases where additional time such as
XPDLL (MIN) is required.
AOF (MAX) are required to be derated by subtracting both
JIT
REF
DTY
(
DC
(MAX).
) and the consecutive crossing of V
t
ERR
t
ADC (MIN) and
10PER
(MAX) and
76
t
AOF (MIN) are each required to be derated by subtract-
t
JIT
DTY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(MAX). The parameters
REF
1Gb: x4, x8, x16 DDR3 SDRAM
(
DC
).
t
©2006 Micron Technology, Inc. All rights reserved.
ERR
t
ERR
t
ADC (MAX) and
Speed Bin Tables
10PER
10PER
(MAX) and
and
t
JIT
DTY
t
WR.