MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 121

IC DDR3 SDRAM 1GBIT 78FBGA

MT41J256M4HX-15E:D TR

Manufacturer Part Number
MT41J256M4HX-15E:D TR
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (256M x 4)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-FBGA
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
220mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MPR Register Address Definitions and Bursting Order
Table 70:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
MR3[2]
1
1
1
1
MPR Readouts and Burst Order Bit Mapping
MR3[1:0]
00
01
10
11
Notes:
pattern for system
READ predefined
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”
The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit
pattern.
Examples of the different types of predefined READ pattern bursts are shown in
Figure 62 on page 122, Figure 63 on page 123, Figure 64 on page 124, and Figure 65 on
page 125.
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected
calibration
MPR agent.
Function
RFU
RFU
RFU
Length
Burst
BL8
BC4
BC4
n/a
n/a
n/a
n/a
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n/a
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121
A[2:0]
Read
000
000
100
n/a
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n/a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
1Gb: x4, x8, x16 DDR3 SDRAM
Burst Order and Data Pattern
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
Predefined pattern: 0, 1, 0, 1
Burst order: 0, 1, 2, 3
Burst order: 4, 5, 6, 7
©2006 Micron Technology, Inc. All rights reserved.
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Operations

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