MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 7

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1Gb: x4, x8, x16 DDR3 SDRAM
List of Figures
Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . . 165
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 116: Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 117: Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 118: ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 119: Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . . 175
Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . . 177
Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . . 179
Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . . 180
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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1Gb_DDR3_LOF.fm - Rev. F 11/08 EN
©2006 Micron Technology, Inc. All rights reserved.