MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 77

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command and Address Setup, Hold, and Derating
Table 54:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
t
IS (base): AC150
t
t
Symbol
IH (base)
IS (base)
Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
DDR3-800
200
275
n/a
The total
sheet
page 67) to the Δ
page 78), respectively. Example:
sition, the input signal has to remain above/below V
(see Table 56 on page 78).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach V
V
between the values listed in Table 56 on page 78 and Table 57 on page 79, the derating
values may be obtained by linear interpolation.
Setup (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of V
and the first crossing of V
nominal slew rate line between the shaded “V
slew rate for derating value (see Figure 35 on page 80). If the actual signal is later than the
nominal slew rate line anywhere between the shaded “V
rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 37 on page 82).
Hold (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of
V
nominal slew rate line between the shaded “DC-to-V
slew rate for derating value (see Figure 36 on page 81). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-V
slew rate of a tangent line to the actual signal from the DC level to the V
used for derating value (see Figure 38 on page 83).
IL
IH
(
(
AC
DC
t
) (see Figure 17 on page 42 for input signal requirements). For slew rates which fall
t
IS (base) and
IH) nominal slew rate for a rising signal is defined as the slew rate between the
) MIN and the first crossing of V
t
IS) nominal slew rate for a rising signal is defined as the slew rate between the
t
DDR3-1066
IS (setup time) and
125
200
n/a
t
REF
IL
IS and Δ
(
DC
(
t
IH (base) values (see Table 54; values come from Table 53 on
DC
) MAX and the first crossing of V
) and the first crossing of V
IL
t
DDR3-1333
IH derating values (see Table 55 on page 78 and Table 56 on
(
AC
77
t
140
190
) MAX. If the actual signal is always earlier than the
65
IH (hold time) required is calculated by adding the data
t
IS (total setup time) =
IH
[
REF
AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
]/V
(
DDR3-1600
DC
IL
). If the actual signal is always later than the
[
REF
120
170
AC
45
1Gb: x4, x8, x16 DDR3 SDRAM
] at the time of the rising clock transi-
(
DC
IH
(
IH
)-to-AC region,” use the nominal
REF
AC
REF
(
t
AC
) MIN. Setup (
IS (base) + Δ
(
REF
DC
(
)/V
DC
(
) region,” use the nominal
Units
DC
). Hold (
IL
ps
ps
ps
(
©2006 Micron Technology, Inc. All rights reserved.
)-to-AC region,” the slew
AC
) for some time
Speed Bin Tables
REF
t
IS. For a valid tran-
t
IH) nominal slew
t
IS) nominal slew
(
DC
REF
V
V
V
) region,” the
Reference
IH
IH
IH
(
(
(
(
DC
AC
DC
AC
) level is
)/V
)/V
)/V
REF
IL
IL
IL
t
IH
(
(
(
(
VAC
DC
AC
DC
AC
(
AC
)
)
)
)
)/