LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 137

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Read: Anytime
Write: Anytime
These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU
or BDM) memory map from address 0x1000 to address 0x1FFF (see
up to 1022KB of RAM (in the Global map) within the 64KB Local map. The RAM page index register is
effectively used to construct paged RAM addresses in the Local map
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
Freescale Semiconductor
RP[7:0]
Field
7–0
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = 0x00.
The page 0xFD (reset value) contains unimplemented area in the range not
occupied by RAM if RAMSIZE is less than 12KB (Refer to
“Implemented Memory
0
0
0
S12XS Family Reference Manual, Rev. 1.11
Figure 3-14. RPAGE Address Mapping
Bit19
Table 3-8. RPAGE Field Descriptions
Global Address [22:0]
Map).
Bit18
RPAGE Register [7:0]
NOTE
NOTE
Description
Bit12
Address: CPU Local Address
Bit11
Figure
or BDM Local Address
format.
Address [11:0]
Memory Mapping Control (S12XMMCV4)
Section 3.4.2.3,
3-14). This supports accessing
Bit0
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