LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 78

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

1
Port Integration Module (S12XSPIMV1)
2.3.9
78
Address 0x0009 (PRR)
6-5, 3-2
Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
Field
Reset
PE
PE
PE
PE
PE
7
4
1
0
W
R
Port E general purpose input/output data—Data Register, ECLKX2 output, XCLKS input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port E general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port E general purpose input/output data—Data Register, ECLK output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port E general purpose input data and interrupt—Data Register, IRQ input.
This pin can be used as general purpose and IRQ input.
Port E general purpose input data and interrupt—Data Register, XIRQ input.
This pin can be used as general purpose and XIRQ input.
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
• The external clock selection feature (XCLKS) is only active during RESET=0
• The ECLK output function takes precedence over the general purpose I/O function if enabled.
DDRE7
Port E Data Direction Register (DDRE)
0
7
= Unimplemented or Reserved
DDRE6
0
6
Figure 2-7. Port E Data Direction Register (DDRE)
Table 2-8. PORTE Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
DDRE5
0
5
DDRE4
0
4
Description
DDRE3
3
0
DDRE2
0
2
Freescale Semiconductor
Access: User read/write
0
0
1
0
0
0
1