LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 224

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

S12X Debug (S12XDBGV3) Module
6.4.5.3.1
The format of the control information byte is dependent upon the active trace mode as described below.
In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control
information. In Detail Mode, CXINF contains the control information
CPU12X Information Byte
CXINF Information Byte
This describes the format of the information byte used only when tracing in Detail Mode. When tracing
from the CPU12X in Detail Mode, information is stored to the trace buffer on all cycles except opcode
fetch and free cycles. In this case the CSZ and CRW bits indicate the type of access being made by the
CPU12X.
224
Field
Field
CSD
CVA
CDV
CSZ
7
6
4
6
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses
are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal
and Loop1 mode tracing. This bit has no meaning in Pure PC mode.
0 Indexed jump destination address
1 Vector destination address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains
valid information when tracing CPU12X activity in Detail Mode.
0 Word Access
1 Byte Access
Information Byte Organization
CSD
Bit 7
Bit 7
Bit 6
Bit 6
CSZ
CVA
Figure 6-23. CPU12X Information Byte CINF
S12XS Family Reference Manual, Rev. 1.11
Table 6-42. CXINF Field Descriptions
Figure 6-24. Information Byte CXINF
Table 6-41. CINF Field Descriptions
CRW
Bit 5
Bit 5
0
Bit 4
CDV
Bit 4
Description
Description
Bit 3
Bit 3
0
Bit 2
Bit 2
0
Bit 1
Bit 1
0
Freescale Semiconductor
Bit 0
Bit 0
0