LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 240

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

S12XE Clocks and Reset Generator (S12XECRGV1)
8.3.2.2
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Read: Anytime
Write: Anytime except when PLLSEL = 1
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
(no locking and/or insufficient stability).
8.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f
(divide by one).
240
Module Base + 0x0001
Reset
W
R
f REF
S12XECRG Reference Divider Register (REFDV)
S12XECRG Post Divider Register (POSTDIV)
0
7
=
REFFRQ[1:0]
Write to this register initializes the lock detector bit.
------------------------------------
(
REFDIV
f OSC
Figure
Figure 8-4. S12XECRG Reference Divider Register (REFDV)
0
6
+
1
)
Table 8-3. Reference Clock Frequency Selection
8-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL
REFCLK Frequency Ranges
S12XS Family Reference Manual, Rev. 1.11
1MHz <= f
6MHz < f
2MHz < f
0
5
f
REF
REF
REF
>12MHz
REF
<= 12MHz
<= 6MHz
<= 2MHz
NOTE
0
4
0
3
REFFRQ[1:0]
REFDIV[5:0]
00
01
10
11
0
2
Freescale Semiconductor
0
1
PLL
= f
0
0
VCO