LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 242

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

S12XE Clocks and Reset Generator (S12XECRGV1)
8.3.2.5
This register enables S12XECRG interrupt requests.
242
Module Base + 0x0004
LOCKIF
SCMIF
Reset
PORF
LOCK
Field
LVRF
SCM
RTIF
ILAF
7
6
5
4
3
2
1
0
W
R
RTIE
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
IPLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.
Writes have no effect.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
S12XECRG Interrupt Enable Register (CRGINT)
0
7
running at its minimum frequency f
= Unimplemented or Reserved
Figure 8-7. S12XECRG Interrupt Enable Register (CRGINT)
0
0
6
S12XS Family Reference Manual, Rev. 1.11
Table 8-4. CRGFLG Field Descriptions
0
0
5
SCM
.
LOCKIE
0
4
Description
0
0
3
0
0
2
SCMIE
Freescale Semiconductor
0
1
0
0
0