LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 54

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Device Overview S12XS Family
1.6.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
1.6.3.4
The RAM arrays are not initialized out of reset.
1.6.3.5
The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded from the Flash
register FOPT. See
configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.
54
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
Memory
COP Configuration
Table 1-11
FOPT Register
FOPT Register
and
NV[2:0] in
Table 1-11. Initial COP Rate Configuration
NV[3] in
Table 1-12. Initial WCOP Configuration
S12XS Family Reference Manual, Rev. 1.11
000
001
010
011
100
101
110
111
Table 1-12
1
0
for coding. The FOPT register is loaded from the Flash
COPCTL Register
COPCTL Register
CR[2:0] in
WCOP in
111
110
101
100
011
010
001
000
0
1
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