LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 371

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts
off for power savings.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0000
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
Reset
Field
7
6
5
4
3
2
W
R
PWME7
Pulse Width Channel 7 Enable
0 Pulse width channel 7 is disabled.
1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when
Pulse Width Channel 6 Enable
0 Pulse width channel 6 is disabled.
1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
0
7
The first PWM cycle after enabling the channel can be irregular.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.
PWME6
0
6
Figure 13-3. PWM Enable Register (PWME)
S12XS Family Reference Manual, Rev. 1.11
Table 13-1. PWME Field Descriptions
PWME5
0
5
PWME4
NOTE
0
4
Description
PWME3
0
3
PWME2
Pulse-Width Modulator (S12PWM8B8CV1)
0
2
PWME1
0
1
PWME0
0
0
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