LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 174

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Background Debug Module (S12XBDMV2)
5.3.2.2
Register Global Address 0x7FFF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
5.3.2.3
Register Global Address 0x7FFF07
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
174
Special Single-Chip Mode
Reset
W
R
All Other Modes
BDM CCR LOW Holding Register (BDMCCRL)
BDM CCR HIGH Holding Register (BDMCCRH)
0
0
7
When BDM is made active, the CPU stores the content of its CCR
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
BDMCCRL register is read zero.
Reset
L
W
= Unimplemented or Reserved
R
register in this CPU mode. Out of reset in all other modes the
Figure 5-5. BDM CCR HIGH Holding Register (BDMCCRH)
Figure 5-4. BDM CCR LOW Holding Register (BDMCCRL)
CCR7
0
0
6
1
0
7
S12XS Family Reference Manual, Rev. 1.11
CCR6
1
0
6
5
0
0
CCR5
0
0
5
NOTE
0
0
4
CCR4
0
0
4
0
0
3
CCR3
1
0
3
CCR10
2
0
CCR2
0
0
2
L
register
Freescale Semiconductor
CCR9
0
1
CCR1
0
0
1
CCR8
CCR0
0
0
0
0
0