LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 528

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

256 KByte Flash Module (S12XFTMR256K1V1)
18.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed.
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
18.3.2.10 D-Flash Protection Register (DFPROT)
The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0D located in P-Flash memory (see
as indicated by reset condition F in
during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be unprotected,
then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the
528
Offset Module Base + 0x0009
Reset
W
R
DPOPEN
F
7
P-Flash Protection Restrictions
1
Protection
Allowed transitions marked with X, see
Scenario
From
= Unimplemented or Reserved
0
1
2
3
4
5
6
7
0
0
6
Table 18-21. P-Flash Protection Scenario Transitions
Figure 18-15. D-Flash Protection Register (DFPROT)
X
X
0
S12XS Family Reference Manual, Rev. 1.11
Figure
0
0
5
X
X
X
X
1
18-15. To change the D-Flash protection that will be loaded
X
X
X
X
2
To Protection Scenario
F
4
Figure 18-14
X
X
X
X
X
X
X
X
3
X
X
X
X
4
for a definition of the scenarios.
F
3
1
5
X
X
DPS[4:0]
F
2
X
X
6
Table 18-21
Freescale Semiconductor
X
7
F
1
Table
specifies
F
0
18-3)